build/dts/api/bindings/clock/st,stm32g0-hsi-clock.html · build/dts/api/bindings/clock/st,stm32g0-hsi-clock.rst 공식 원문 ↗

Zephyr 3.7.0 · Devicetree · Clock · STMicroelectronics

STM32G0 HSI binding

3개 property로 G0 HSI16 to HSISYS schema를 정의합니다.

Official pathbuild/dts/api/bindings/clock/st,stm32g0-hsi-clock.html
Source filebuild/dts/api/bindings/clock/st,stm32g0-hsi-clock.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

공식 원문 105줄과 property 3행을 전수 대조해 Description·수식과 type·required·constant·default·legal value를 보존했습니다.

Compatible

st,stm32g0-hsi-clock

Vendor

STMicroelectronics

Properties

3 rows

Schema

G0 HSI16 to HSISYS

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 3584C32B96ED9FFD81578FBAE74F51310E812F406769BD1A59E0701B9FE6D5D4
:orphan:

.. raw:: html

    <!--
    FIXME: do not limit page width until content uses another representation
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.. dtcompatible:: st,stm32g0-hsi-clock
.. _dtbinding_st_stm32g0_hsi_clock:

st,stm32g0-hsi-clock
####################

Vendor: :ref:`STMicroelectronics <dt_vendor_st>`

Description
***********



.. code-block:: none

   STM32 HSI Clock node description for STM32G0 devices
   On STM32G0, HSI is a 16MHz fixed clock.

   It also produces a HSISYS secondary clk which can be used as system clock
   source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
   SYSCLK = HSI16 / HSI DIV
         enum:
         - 1 ==> HSISYS = 16MHZ
         - 2 ==> HSISYS = 8MHZ
         - 4 ==> HSISYS = 4MHZ
         - 8 ==> HSISYS = 2MHZ
         - 16 ==> HSISYS = 1MHZ
         - 32 ==> HSISYS = 0.5MHz
         - 64 ==> HSISYS = 0.25MHZ
         - 128 ==> HSISYS = 0.125MHz

Properties
**********

.. tabs::

   .. group-tab:: Node specific properties

      Properties not inherited from the base binding file.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``#clock-cells``
           - ``int``
           - .. code-block:: none

                Number of items to expect in a Clock specifier


             This property is **required**.

         * - ``clock-frequency``
           - ``int``
           - .. code-block:: none

                output clock frequency (Hz)


             This property is **required**.

         * - ``hsi-div``
           - ``int``
           - .. code-block:: none

                HSI clock divider. Configures the output HSI clock frequency (HSISYS),
                It does not apply to HSI clk selected as peripheral source clock
                (eg: RNG clk driven by HSI)



             This property is **required**.

             Legal values: ``1``, ``2``, ``4``, ``8``, ``16``, ``32``, ``64``, ``128``



   .. group-tab:: Deprecated node specific properties

      Deprecated properties not inherited from the base binding file.

      (None)

   .. group-tab:: Base properties

      Properties inherited from the base binding file, which defines
      common properties that may be set on many nodes. Not all of these
      may apply to the "st,stm32g0-hsi-clock" compatible.

      (None)


Part 3

한국어 전문 번역

st,stm32g0-hsi-clock

Vendor: STMicroelectronics

공식 설명

STM32 HSI Clock node description for STM32G0 devices
On STM32G0, HSI is a 16MHz fixed clock.

It also produces a HSISYS secondary clk which can be used as system clock
source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
SYSCLK = HSI16 / HSI DIV
      enum:
      - 1 ==> HSISYS = 16MHZ
      - 2 ==> HSISYS = 8MHZ
      - 4 ==> HSISYS = 4MHZ
      - 8 ==> HSISYS = 2MHZ
      - 16 ==> HSISYS = 1MHZ
      - 32 ==> HSISYS = 0.5MHz
      - 64 ==> HSISYS = 0.25MHZ
      - 128 ==> HSISYS = 0.125MHz

16 MHz HSI와 HSISYS

고정 16 MHz HSI에서 SYSCLK = HSI16 / hsi-div로 system clock용 HSISYS를 만듭니다. Divider 1·2·4·8·16·32·64·128은 각각 16·8·4·2·1·0.5·0.25·0.125 MHz입니다.

hsi-div는 RNG처럼 HSI를 peripheral source로 직접 선택한 경우에는 적용되지 않습니다. #clock-cells, clock-frequency, hsi-div가 모두 필수이며 base property 표는 없습니다.

Property

Zephyr 3.7.0 공식 스키마의 모든 속성을 실었습니다. 자료형, 필수 여부, 사용 중단 여부, 상수, 기본값, 허용값은 원문에서 가져왔습니다.

노드 전용 속성 · 3개
이름형식설명과 제약
#clock-cellsintConsumer의 clock specifier에서 기대할 item 수입니다.
필수
clock-frequencyintClock output frequency를 Hz 단위로 지정합니다.
필수
hsi-divintHSI에서 system clock용 HSISYS를 만드는 divider입니다. Peripheral source로 직접 선택한 HSI에는 적용되지 않습니다.
필수 · 허용값: 1, 2, 4, 8, 16, 32, 64, 128

Source

출처

영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.