Part 1
요약·해설
A53와 M4 target의 지원 기능을 분리하고, U-Boot·SMP·Jailhouse A53 실행과 M4 RAM mapping·A53 주도 boot·JTAG debug 절차를 설명합니다.
4× Cortex-A53 · 1× Cortex-M4
2 GB LPDDR4 · eMMC · QSPI
U-Boot · Jailhouse · bootaux
Part 2
접을 수 있는 영어 원문 전체
영어 원문 전체 펼치기
BDCE158919D42CA4FAE3901AD102B79F2D20CCBFE4D705E41432EAB55523E206
.. _imx8mm_evk:
NXP i.MX8MM EVK
###############
Overview
********
i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications
processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
- Board features:
- RAM: 2GB LPDDR4
- Storage:
- SanDisk 16GB eMMC5.1
- Micron 32MB QSPI NOR
- microSD Socket
- Wireless:
- WiFi: 2.4/5GHz IEEE 802.11b/g/n
- Bluetooth: v4.1
- USB:
- OTG - 2x type C
- Ethernet
- PCI-E M.2
- Connectors:
- 40-Pin Dual Row Header
- LEDs:
- 1x Power status LED
- 1x UART LED
- Debug
- JTAG 20-pin connector
- MicroUSB for UART debug, two COM ports for A53 and M4
More information about the board can be found at the
`NXP website`_.
Supported Features
==================
The Zephyr imx8mm_evk board for Cortex-A53 configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| GIC-v3 | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | GPIO output |
| | | GPIO input |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig`
It is recommended to disable peripherals used by the M4 core on the Linux host.
Other hardware features are not currently supported by the port.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 8 MHz.
The M4 Core is configured to run at a 400 MHz clock speed.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART4. This is used for the M4 and A53 core targets.
Programming and Debugging (A53)
*******************************
Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and kick zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000
Or kick SMP zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: imx8mm_evk/mimx8mm6/a53
:goals: run
This will build an image with the synchronization sample app, boot it and
display the following ram console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 ***
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
Use Jailhouse hypervisor, after root cell linux is up:
.. code-block:: console
#jailhouse enable imx8mm.cell
#jailhouse cell create imx8mm-zephyr.cell
#jailhouse cell load 1 zephyr.bin -a 0x93c00000
#jailhouse cell start 1
Programming and Debugging (M4)
******************************
The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs
to be started by the A53 core. The A53 core is responsible to load the M4 binary
application into the RAM, put the M4 in reset, set the M4 Program Counter and
Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at
bootloader level or after the Linux system has booted.
The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4:
+------------+-------------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size |
+============+=========================+========================+=======================+======================+
| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
For more information about memory mapping see the
`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3)
At compilation time you have to choose which RAM will be used. This
configuration is done in the file
:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts`
with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties.
The available configurations are:
.. code-block:: none
"zephyr,flash"
- &tcml_code
- &ocram_code
- &ocram_s_code
"zephyr,sram"
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys
Load and run Zephyr on M4 from A53 using u-boot by copying the compiled
``zephyr.bin`` to the first FAT partition of the SD card and plug the SD
card into the board. Power it up and stop the u-boot execution at prompt.
Load the M4 binary onto the desired memory and start its execution using:
.. code-block:: console
fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000
Debugging
=========
MIMX8MM EVK board can be debugged by connecting an external JLink
JTAG debugger to the J902 debug connector and to the PC. Then
the application can be debugged using the usual way.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: imx8mm_evk/mimx8mm6/m4
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 *****
Hello World! imx8mm_evk
References
==========
.. _NXP website:
https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK
.. _i.MX 8M Applications Processor Reference Manual:
https://www.nxp.com/webapp/Download?colCode=IMX8MMRM
Part 3
한국어 전문 번역
개요
i.MX8M Mini LPDDR4 EVK는 NXP i.MX8M Mini application processor 기반 보드입니다. processor는 quad Cortex-A53 cluster와 single Cortex-M4 core로 구성되며 Zephyr OS는 Cortex-A53 core에서도 실행되도록 port되어 있습니다.
보드 기능
- 2 GB LPDDR4 RAM
- SanDisk 16 GB eMMC 5.1, Micron 32 MB QSPI NOR, microSD socket
- 2.4/5 GHz IEEE 802.11b/g/n Wi-Fi와 Bluetooth v4.1
- USB OTG Type-C 2개, Ethernet, PCIe M.2
- 40-pin dual-row header
- power status LED 1개와 UART LED 1개
- 20-pin JTAG connector
- A53/M4 각각의 COM port를 제공하는 UART debug용 MicroUSB
지원 기능
Cortex-A53 configuration
| 인터페이스 | 컨트롤러 | 드라이버/컴포넌트 |
|---|---|---|
GIC-v3 | on-chip | interrupt controller |
ARM TIMER | on-chip | system clock |
UART | on-chip | serial port |
Cortex-M4 configuration
| 인터페이스 | 컨트롤러 | 드라이버/컴포넌트 |
|---|---|---|
NVIC | on-chip | nested vector interrupt controller |
SYSTICK | on-chip | systick |
CLOCK | on-chip | clock_control |
PINMUX | on-chip | pinmux |
UART | on-chip | serial port-polling; serial port-interrupt |
GPIO | on-chip | GPIO output; GPIO input |
기본 구성은 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig에 있습니다. Linux host에서는 M4 core가 사용하는 peripheral을 비활성화하는 것이 권장됩니다.
Device
System clock
board configuration의 system clock frequency는 8 MHz이며 M4 core는 400 MHz로 동작합니다.
Serial port
M4와 A53 target 모두 CPU의 UART4 하나를 serial communication channel로 사용합니다.
A53 프로그래밍과 디버깅
compile된 zephyr.bin을 SD card 첫 번째 FAT partition에 복사하고 보드에 꽂은 뒤, 전원을 켜고 U-Boot prompt에서 실행을 중지합니다.
단일 image 기동
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000SMP image 기동
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000
기본 Zephyr application과 kernel test는 samples/synchronization 예제로 실행할 수 있습니다.
west build -b imx8mm_evk/mimx8mm6/a53 samples/synchronization
west build -t runimage를 build하고 boot하면 RAM console에 다음과 같은 출력이 나타납니다.
*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 ***
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mm_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mm_evk_a53!
Jailhouse 사용
root-cell Linux가 기동한 뒤 다음과 같이 Zephyr cell을 시작합니다.
jailhouse enable imx8mm.cell
jailhouse cell create imx8mm-zephyr.cell
jailhouse cell load 1 zephyr.bin -a 0x93c00000
jailhouse cell start 1
M4 프로그래밍과 디버깅
MIMX8MM EVK에는 M4용 QSPI flash가 없으므로 A53 core가 M4를 시작해야 합니다. A53은 M4 binary를 RAM에 load하고 M4를 reset 상태로 만든 뒤 Program Counter와 Stack Pointer를 설정하고 reset에서 해제합니다. bootloader 단계나 Linux boot 이후에 이 작업을 수행할 수 있습니다.
M4가 사용할 수 있는 세 종류 RAM의 A53/M4 memory mapping은 다음과 같습니다.
| 영역 | Cortex-A53 | Cortex-M4 System Bus | Cortex-M4 Code Bus | 크기 |
|---|---|---|---|---|
OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256 KB |
TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | - | 128 KB |
TCML | 0x007E0000-0x007FFFFF | - | 0x1FFE0000-0x1FFFFFFF | 128 KB |
OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32 KB |
자세한 mapping은 i.MX 8M Applications Processor Reference Manual 2.1.2와 2.1.3절을 참고하십시오.
compile 시 사용할 RAM을 선택해야 합니다. boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts에서 CONFIG_XIP=y일 때의 zephyr,flash와 zephyr,sram property로 구성합니다.
zephyr,flash
- &tcml_code
- &ocram_code
- &ocram_s_code
zephyr,sram
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys
zephyr.bin을 SD card 첫 FAT partition에 복사하고 U-Boot prompt에서 원하는 memory에 load해 실행합니다.
fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000
M4 debug
external J-Link JTAG debugger를 J902 debug connector와 PC에 연결해 일반적인 방식으로 debug할 수 있습니다.
west build -b imx8mm_evk/mimx8mm6/m4 samples/hello_world
west debugdebugger에서 단계 실행하면 다음 출력이 나타납니다.
***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 *****
Hello World! imx8mm_evk
참고 자료
Source
출처
영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.