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Zephyr 3.7.0 · Boards · Intel SoC FPGA

Intel Agilex 5 SoC FPGA Development Kit

Dual A55·dual A76과 DDR5를 통합한 Agilex 5 SoC FPGA development kit입니다.

Official pathboards/intel/socfpga/agilex5_socdk/doc/index.html
Source fileboards/intel/socfpga/agilex5_socdk/doc/index.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

Agilex 5 E-Series FPGA, 8GB DDR5, GIC-600과 ATF boot flow를 설명합니다.

CPUs

2x A55 · 2x A76

Memory

8GB DDR5

Load

0x80000000

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 BADD364F8394A51F501908087C934DA1A17DE3AA94A372951019DDA56AE4112E 
.. _intel_socfpga_agilex5_socdk:

Intel® Agilex™ 5 SoC FPGA Development Kit
#########################################

Overview
********

The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design
environment that includes both hardware and software for developing
Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for
developing custom ARM* processor-based SoC designs and ideal for intelligent
applications at the edge, embedded and more.

Hardware
********

The Intel® Agilex™ 5 Development Kit supports the following physical features:

- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with
  multi-core ARM processors of Dual-core A55 and Dual-core A76
- On-board 8 GB DDR5 memory
- On-board JTAG Intel FPGA Download Cable II
- QSPI flash daughtercard

Supported Features
==================
The Intel® Agilex™ 5 SoC Development Kit configuration supports the following
hardware features:

+-----------+------------+---------------------------------------------+
| Interface | Controller | Hardware Subsystem Vendor                   |
+===========+============+=============================================+
| GIC-600   | on-chip    | ARM GICv3 interrupt controller              |
+-----------+------------+---------------------------------------------+
| UART      | on-chip    | Synopsys Designware,NS16550 compatible      |
+-----------+------------+---------------------------------------------+
| ARM TIMER | on-chip    | ARM system timer                            |
+-----------+------------+---------------------------------------------+
| Reset     | on-chip    | Intel Corporation, SoCFPGA Reset controller |
+-----------+------------+---------------------------------------------+
| Clock     | on-chip    | Intel Corporation, SoCFPGA Clock controller |
+-----------+------------+---------------------------------------------+

NOTE: TODO, more details on dev kit will be updated as and when available.

The default configuration can be found in the defconfig file:
        `boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig`

Programming and Debugging
*************************

Zephyr Boot Flow
****************
Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF).
ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which
provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface).

Boot flow:
        ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1)

Intel Arm Trusted Firmware (ATF) can be downloaded from github:
        `altera-opensource/arm-trusted-firmware <https://github.com/altera-opensource/arm-trusted-firmware.git>`_

Flashing
========
Zephyr image can be loaded in DDR memory at address 0x80000000 from
SD Card or QSPI Flash or NAND in ATF BL2.

Debugging
=========
The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on
board, connect it to Intel USB blaster download cables for debugging.

Zephyr applications running on the Cortex-A55/A76 core can be tested by
observing UART console output.

References
==========
`Intel® Agilex™ 5 FPGA and SoC FPGA <https://www.intel.in/content/www/in/en/products/details/fpga/agilex/5.html>`_

Part 3

한국어 전문 번역

개요

Intel Agilex 5 SoC FPGA Development Kit는 Intel Agilex 5 E-Series 기반 FPGA design 개발에 필요한 hardware와 software를 포함한 complete design environment를 제공합니다. Custom Arm processor 기반 SoC design 개발에 권장되며 edge intelligent application과 embedded application 등에 적합합니다.

Hardware

  • 50K~656K logic element(LE)와 dual-core Cortex-A55 및 dual-core Cortex-A76 multi-core Arm processor를 통합한 Intel Agilex 5 E-Series FPGA
  • Onboard 8GB DDR5 memory
  • Onboard JTAG Intel FPGA Download Cable II
  • QSPI flash daughtercard

지원 기능

InterfaceControllerHardware Subsystem Vendor
GIC-600on-chipARM GICv3 interrupt controller
UARTon-chipSynopsys DesignWare, NS16550 compatible
ARM TIMERon-chipARM system timer
Reseton-chipIntel Corporation, SoCFPGA Reset controller
Clockon-chipIntel Corporation, SoCFPGA Clock controller

Default configuration은 boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig에 있습니다.

Programming과 Debugging

Zephyr boot flow

Zephyr image는 Intel Arm Trusted Firmware(ATF)가 load해야 합니다. ATF BL2는 First Stage Boot Loader(FSBL)이고 ATF BL31은 runtime resident firmware로 SMC(Secure Monitor Call)와 PSCI(Power State Coordination Interface) 같은 service를 제공합니다.

ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1)

Intel ATF는 altera-opensource/arm-trusted-firmware에서 받을 수 있습니다.

Flashing

ATF BL2가 SD card, QSPI flash 또는 NAND에서 Zephyr image를 DDR address 0x80000000에 load할 수 있습니다.

Debugging

Board의 JTAG connector를 Intel USB Blaster download cable에 연결해 debug합니다. Cortex-A55/A76 core에서 실행되는 Zephyr application은 UART console output으로 시험할 수 있습니다.

참고 자료

Intel Agilex 5 FPGA and SoC FPGA

Source

출처

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