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Zephyr 3.7.0 · Boards · Intel FPGA · Nios V

Intel FPGA Nios V/g

Intel FPGA의 Nios V/g processor에서 Zephyr ELF를 실행하는 절차입니다.

Official pathboards/intel/niosv_g/doc/index.html
Source fileboards/intel/niosv_g/doc/index.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

Nios V/g processor, JTAG UART와 on-chip memory로 구성된 FPGA example system입니다.

Processor

Nios V/g

FPGA file

top.sof

Runtime

JTAG UART

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 4667BEFD00BCB73F08EF0A47D27965CD33A43B283F0F4A7CCC1F51B840A541D8
.. _niosv_g:

INTEL FPGA niosv_g
####################

Overview
********

niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and this complete system is consisted of following IP blocks:

.. code-block:: console

	Nios® V/g Processor Intel® FPGA IP
	JTAG UART Intel® FPGA IP
	On-Chip Memory Intel® FPGA IP

Nios® V/g hello world example design system
===========================================

Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
- https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?s=Newest

For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded from following link.
- https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html

ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system after the downloaded PAR files extracted successfully.

Create Nios® V/g processor example design system in FPGA
========================================================

Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA and execute application.

In order to create the Nios® V/g processor inside the FPGA device, please download the generated .sof file onto the board with the following command.

.. code-block:: console

	quartus_pgm -c 1 -m JTAG -o "p;top.sof@1"

.. code-block:: console

	Note:
	-c 1 is referring to JTAG cable number connected to the Host Computer.
	@1 is referring to device index on the JTAG Chain and may differ for your board.
	top.sof is referring to Nios® V/m processor based system SRAM Object File.

Download Zephyr elf file and run application
============================================

To download the Zephyr Executable and Linkable Format .elf file, please use the niosv-download command within Nios V Command Shell environment.

.. code-block:: console

	niosv-download -g <elf file>

Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/g processor system.

.. code-block:: console

	juart-terminal

Similar message shown below should be appeared in the JTAG UART terminal when using hello world sample code:

.. code-block:: console

	*** Booting Zephyr OS build zephyr-vn.n.nn  ***
	Hello World! niosv_g

Part 3

한국어 전문 번역

개요

niosv_g board는 Intel FPGA Design Store의 Nios® V/g Hello World Example Design system을 기반으로 합니다. 전체 system은 다음 IP block으로 구성됩니다.

Nios® V/g Processor Intel® FPGA IP
JTAG UART Intel® FPGA IP
On-Chip Memory Intel® FPGA IP

Nios® V/g Hello World example design system

Prebuilt Nios® V/g Hello World example design system은 Intel FPGA Design Store에서 받을 수 있습니다. Arria 10용 prebuilt file 예시는 공식 Nios® V/g example design에서 내려받습니다.

내려받은 PAR file을 정상적으로 압축 해제하면 ready_to_test/top.sof가 Hello World example design system용 prebuilt SRAM Object File입니다.

FPGA에 Nios® V/g example design system 생성

Intel Quartus Programmer tool로 Nios® V/g processor 기반 system을 FPGA에 programming하고 application을 실행합니다. 생성된 .sof file을 다음 명령으로 board에 내려받아 FPGA device 안에 Nios® V/g processor를 만듭니다.

quartus_pgm -c 1 -m JTAG -o "p;top.sof@1"
Note:
-c 1 is referring to JTAG cable number connected to the Host Computer.
@1 is referring to device index on the JTAG Chain and may differ for your board.
top.sof is referring to Nios® V/m processor based system SRAM Object File.

-c 1은 host computer에 연결된 JTAG cable number입니다. @1은 JTAG chain의 device index이며 board마다 다를 수 있습니다. 원문 note는 top.sof를 Nios® V/m processor 기반 system의 SRAM Object File이라고 설명합니다.

Zephyr ELF 내려받기와 application 실행

Zephyr Executable and Linkable Format .elf file을 내려받으려면 Nios V Command Shell environment에서 niosv-download를 사용합니다.

niosv-download -g <elf file>

JTAG UART terminal로 Nios® V/g processor system의 stdout과 stderr를 출력합니다.

juart-terminal

Hello World sample을 사용하면 JTAG UART terminal에 다음과 비슷한 message가 나타납니다.

*** Booting Zephyr OS build zephyr-vn.n.nn  ***
Hello World! niosv_g

Source

출처

영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.