← Documents Documentation/virt/kvm/devices/xics.rst GitHub 원문 ↗

Linux 6.18.37 · 가상화 / KVM / Device

XICS interrupt controller

PAPR XICS의 ICP server와 interrupt-source 64-bit migration state를 정의합니다.

Source pathDocumentation/virt/kvm/devices/xics.rst
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

요약·해설

xics.rst:1-92

PAPR XICS의 ICP server와 interrupt-source 64-bit migration state를 정의합니다.

구조체, register field, priority, error code와 migration 순서는 원문 표기를 유지했습니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 .. SPDX-License-Identifier: GPL-2.0
2
3 =========================
4 XICS interrupt controller
5 =========================
6
7 Device type supported: KVM_DEV_TYPE_XICS
8
9 Groups:
10 1. KVM_DEV_XICS_GRP_SOURCES
11 Attributes:
12
13 One per interrupt source, indexed by the source number.
14 2. KVM_DEV_XICS_GRP_CTRL
15 Attributes:
16
17 2.1 KVM_DEV_XICS_NR_SERVERS (write only)
18
19 The kvm_device_attr.addr points to a __u32 value which is the number of
20 interrupt server numbers (ie, highest possible vcpu id plus one).
21
22 Errors:
23
24 ======= ==========================================
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
28 ======= ==========================================
29
30 This device emulates the XICS (eXternal Interrupt Controller
31 Specification) defined in PAPR. The XICS has a set of interrupt
32 sources, each identified by a 20-bit source number, and a set of
33 Interrupt Control Presentation (ICP) entities, also called "servers",
34 each associated with a virtual CPU.
35
36 The ICP entities are created by enabling the KVM_CAP_IRQ_ARCH
37 capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and
38 the interrupt server number (i.e. the vcpu number from the XICS's
39 point of view) in args[1] of the kvm_enable_cap struct. Each ICP has
40 64 bits of state which can be read and written using the
41 KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
42 state word has the following bitfields, starting at the
43 least-significant end of the word:
44
45 * Unused, 16 bits
46
47 * Pending interrupt priority, 8 bits
48 Zero is the highest priority, 255 means no interrupt is pending.
49
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
51 Zero is the highest priority, 255 means no IPI is pending.
52
53 * Pending interrupt source number, 24 bits
54 Zero means no interrupt pending, 2 means an IPI is pending
55
56 * Current processor priority, 8 bits
57 Zero is the highest priority, meaning no interrupts can be
58 delivered, and 255 is the lowest priority.
59
60 Each source has 64 bits of state that can be read and written using
61 the KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the
62 KVM_DEV_XICS_GRP_SOURCES attribute group, with the attribute number being
63 the interrupt source number. The 64 bit state word has the following
64 bitfields, starting from the least-significant end of the word:
65
66 * Destination (server number), 32 bits
67
68 This specifies where the interrupt should be sent, and is the
69 interrupt server number specified for the destination vcpu.
70
71 * Priority, 8 bits
72
73 This is the priority specified for this interrupt source, where 0 is
74 the highest priority and 255 is the lowest. An interrupt with a
75 priority of 255 will never be delivered.
76
77 * Level sensitive flag, 1 bit
78
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
80 edge-sensitive (or MSI).
81
82 * Masked flag, 1 bit
83
84 This bit is set to 1 if the interrupt is masked (cannot be delivered
85 regardless of its priority), for example by the ibm,int-off RTAS
86 call, or 0 if it is not masked.
87
88 * Pending flag, 1 bit
89
90 This bit is 1 if the source has a pending interrupt, otherwise 0.
91
92 Only one XICS instance may be created per VM.
93

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

XICS source와 ICP server

1-53

`KVM_DEV_TYPE_XICS`는 PAPR의 eXternal Interrupt Controller Specification을 emulate합니다. VM에는 instance 하나만 만들 수 있으며 20-bit source number로 식별되는 interrupt source와 vCPU별 Interrupt Control Presentation(ICP) server를 가집니다.

`KVM_DEV_XICS_GRP_SOURCES` attribute는 source number로 index합니다. `KVM_DEV_XICS_GRP_CTRL / KVM_DEV_XICS_NR_SERVERS`는 highest possible vCPU ID+1에 해당하는 interrupt server 수를 `__u32`로 설정합니다.

XICS server-count error
Error조건
`-EINVAL``KVM_MAX_VCPU_IDS`보다 큰 값
`-EFAULT`잘못된 `attr->addr`
`-EBUSY`이미 vCPU가 device에 연결됨

vCPU 연결 전 server topology를 고정합니다.

각 vCPU에서 `KVM_CAP_IRQ_ARCH`를 enable하고 `args[0]=KVM_CAP_IRQ_XICS`, `args[1]=interrupt server number`를 전달해 ICP를 만듭니다. ICP 64-bit state는 vCPU의 `KVM_GET_ONE_REG`·`KVM_SET_ONE_REG`로 migration할 수 있습니다.

XICS ICP 64-bit state
Field폭의미
Unused16예약
Pending interrupt priority80 highest, 255는 pending interrupt 없음
Pending IPI priority80 highest, 255는 pending IPI 없음
Pending source number240은 없음, 2는 IPI
Current processor priority80 highest라 delivery 차단, 255 lowest

Least-significant bit부터 배치된 field입니다.

.. SPDX-License-Identifier: GPL-2.0

=========================
XICS interrupt controller
=========================

Device type supported: KVM_DEV_TYPE_XICS

Groups:
  1. KVM_DEV_XICS_GRP_SOURCES
       Attributes:

         One per interrupt source, indexed by the source number.
  2. KVM_DEV_XICS_GRP_CTRL
       Attributes:

         2.1 KVM_DEV_XICS_NR_SERVERS (write only)

  The kvm_device_attr.addr points to a __u32 value which is the number of
  interrupt server numbers (ie, highest possible vcpu id plus one).

  Errors:

    =======  ==========================================
    -EINVAL  Value greater than KVM_MAX_VCPU_IDS.
    -EFAULT  Invalid user pointer for attr->addr.
    -EBUSY   A vcpu is already connected to the device.
    =======  ==========================================

This device emulates the XICS (eXternal Interrupt Controller
Specification) defined in PAPR.  The XICS has a set of interrupt
sources, each identified by a 20-bit source number, and a set of
Interrupt Control Presentation (ICP) entities, also called "servers",
each associated with a virtual CPU.

The ICP entities are created by enabling the KVM_CAP_IRQ_ARCH
capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and
the interrupt server number (i.e. the vcpu number from the XICS's
point of view) in args[1] of the kvm_enable_cap struct.  Each ICP has
64 bits of state which can be read and written using the
KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu.  The 64 bit
state word has the following bitfields, starting at the
least-significant end of the word:

* Unused, 16 bits

* Pending interrupt priority, 8 bits
  Zero is the highest priority, 255 means no interrupt is pending.

* Pending IPI (inter-processor interrupt) priority, 8 bits
  Zero is the highest priority, 255 means no IPI is pending.

* Pending interrupt source number, 24 bits

XICS interrupt-source state

54-92

각 source의 64-bit state는 `KVM_DEV_XICS_GRP_SOURCES`와 source number attribute를 사용한 `KVM_GET_DEVICE_ATTR`·`KVM_SET_DEVICE_ATTR`로 읽고 씁니다.

XICS source 64-bit state
Field폭의미
Destination32Interrupt를 받을 vCPU의 XICS server number
Priority80 highest, 255 lowest이며 255 source는 delivery되지 않음
Level-sensitive11 level, 0 edge 또는 MSI
Masked11이면 priority와 무관하게 delivery 불가
Pending11이면 pending interrupt 존재

Least-significant end부터 destination과 delivery state가 배치됩니다.

Masked bit는 `ibm,int-off` RTAS call 등으로 source를 차단한 상태를 보존합니다.

  Zero means no interrupt pending, 2 means an IPI is pending

* Current processor priority, 8 bits
  Zero is the highest priority, meaning no interrupts can be
  delivered, and 255 is the lowest priority.

Each source has 64 bits of state that can be read and written using
the KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the
KVM_DEV_XICS_GRP_SOURCES attribute group, with the attribute number being
the interrupt source number.  The 64 bit state word has the following
bitfields, starting from the least-significant end of the word:

* Destination (server number), 32 bits

  This specifies where the interrupt should be sent, and is the
  interrupt server number specified for the destination vcpu.

* Priority, 8 bits

  This is the priority specified for this interrupt source, where 0 is
  the highest priority and 255 is the lowest.  An interrupt with a
  priority of 255 will never be delivered.

* Level sensitive flag, 1 bit

  This bit is 1 for a level-sensitive interrupt source, or 0 for
  edge-sensitive (or MSI).

* Masked flag, 1 bit

  This bit is set to 1 if the interrupt is masked (cannot be delivered
  regardless of its priority), for example by the ibm,int-off RTAS
  call, or 0 if it is not masked.

* Pending flag, 1 bit

  This bit is 1 if the source has a pending interrupt, otherwise 0.

Only one XICS instance may be created per VM.