Part 1
요약·해설
ARC 5개 family의 16개 기능과 GNU·MetaWare toolchain, QEMU·nSIM simulator 상태를 Y/N/WIP/TBD/N/A로 비교합니다.
Families
EM · HS3x/4x · VPX · HS5x · HS6x
Kernel
cache · interrupt · SMP · MPU/MMU
Tools
GNU · MetaWare · QEMU · nSIM
Part 2
접을 수 있는 영어 원문 전체
영어 원문 전체 펼치기
원문 SHA-256
581FD2B0F30D9790A859992F2ADDB30D9493056F1B3A50CCC8C9E77527F46FA9
.. _hardware_arch_arc_support_status:
Zephyr support status on ARC processors
#######################################
Overview
********
This page describes current state of Zephyr for ARC processors and some future
plans. Please note that
* plans are given without exact deadlines
* software features require corresponding hardware to be present and
configured the proper way
* not all the features can be enabled at the same time
Support status
**************
Legend:
**Y** - yes, supported; **N** - no, not supported; **WIP** - Work In Progress;
**TBD** - to be decided
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| | **Processor families** |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| | **EM** | **HS3x/4x** | **VPX** | **HS5x** | **HS6x** |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Port status | upstreamed | upstreamed | upstreamed [#f6]_ | upstreamed | upstreamed |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| **Features** |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | Y | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Hardware-assisted unaligned memory access | Y [#f2]_ | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Regular interrupts with multiple priority levels, direct interrupts | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N | N |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Hardware floating point unit (FPU) | Y | Y | TBD [#f6]_ | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Hardware-assisted stack checking | Y | Y | Y | N | N |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Hardware-assisted atomic operations | N/A | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| DSP ISA | Y | N [#f3]_ | TBD [#f6]_ | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| DSP AGU/XY extensions | Y | N [#f3]_ | N/A | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Userspace | Y | Y | N | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Memory protection unit (MPU) | Y | Y | TBD | N | N |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Memory management unit (MMU) | N/A | N | TBD | N | N |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| SecureShield | Y | N/A | N/A | N/A | N/A |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| Single-thread kernel support [#f5]_ | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| **Toolchains** |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| GNU (open source GCC-based) | Y | Y | N | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| MetaWare (proprietary Clang-based) | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| **Simulators** |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| QEMU (open source) [#f4]_ | Y | Y | N | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
| nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
Notes
*****
.. [#f1] usage of CCMs is limited on SMP systems
.. [#f2] except the systems with secure features (SecureShield) due to HW
limitation
.. [#f3] We only support save/restore ACCL/ACCH registers in task's context.
Rest of DSP/AGU registers save/restore isn't implemented but kernel
itself does not use these registers. This allows single task per
core to use DSP/AGU safely.
.. [#f4] QEMU doesn't support all the ARC processor's HW features. For the
detailed info please check the ARC QEMU documentation
.. [#f5] Single-thread kernel is support only for single core targets
.. [#f6] currently only ARC VPX scalar port is supported. The support of VPX vector pipeline, VCCM,
STU is not included in this port, and require additional development and / or other runtime
integration.
Part 3
한국어 전문 번역
개요
이 페이지는 ARC processor용 Zephyr의 현재 상태와 향후 계획 일부를 설명합니다.
- 계획에는 정확한 deadline이 정해져 있지 않습니다.
- Software 기능을 사용하려면 대응하는 hardware가 존재하고 올바르게 구성돼야 합니다.
- 모든 기능을 동시에 활성화할 수 있는 것은 아닙니다.
지원 상태
표의 기호는 Y=지원, N=미지원, WIP=작업 중, TBD=결정 예정, N/A=해당 없음입니다.
| 항목 | Processor family | ||||
|---|---|---|---|---|---|
| EM | HS3x/4x | VPX | HS5x | HS6x | |
| Port 상태 | upstreamed | upstreamed | upstreamed 6 | upstreamed | upstreamed |
| 기능 | |||||
| Closely coupled memory(ICCM, DCCM) 1 | Y | Y | Y | TBD | TBD |
| Cache를 사용한 실행: instruction/data, L1/L2 cache | Y | Y | Y | Y | Y |
| Hardware 지원 unaligned memory access | Y 2 | Y | Y | Y | Y |
| 여러 priority level의 일반 interrupt와 direct interrupt | Y | Y | Y | Y | Y |
| Fast interrupt와 fast interrupt용 별도 register bank | Y | Y | TBD | N | N |
| Hardware floating point unit(FPU) | Y | Y | TBD 6 | TBD | TBD |
| Switch 기반 symmetric multiprocessing(SMP) | N/A | Y | TBD | Y | Y |
| Hardware 지원 stack 검사 | Y | Y | Y | N | N |
| Hardware 지원 atomic operation | N/A | Y | Y | Y | Y |
| DSP ISA | Y | N 3 | TBD 6 | TBD | TBD |
| DSP AGU/XY extension | Y | N 3 | N/A | TBD | TBD |
| Userspace | Y | Y | N | TBD | TBD |
| Memory protection unit(MPU) | Y | Y | TBD | N | N |
| Memory management unit(MMU) | N/A | N | TBD | N | N |
| SecureShield | Y | N/A | N/A | N/A | N/A |
| Single-thread kernel 5 | Y | Y | Y | Y | Y |
| Toolchain | |||||
| GNU(open source GCC 기반) | Y | Y | N | Y | Y |
| MetaWare(proprietary Clang 기반) | Y | Y | Y | Y | Y |
| Simulator | |||||
| QEMU(open source) 4 | Y | Y | N | Y | Y |
| nSIM(proprietary, MetaWare Development Tools 제공) | Y | Y | Y | Y | Y |
주석
- CCM 사용은 SMP system에서 제한됩니다.
- Hardware 제한 때문에 SecureShield 같은 secure 기능이 있는 system은 hardware 지원 unaligned memory access의 예외입니다.
- 현재 task context에서 ACCL/ACCH register의 save·restore만 지원합니다. 나머지 DSP/AGU register의 save·restore는 구현되지 않았지만 kernel 자체는 이 register를 사용하지 않습니다. 따라서 core당 하나의 task는 DSP/AGU를 안전하게 사용할 수 있습니다.
- QEMU는 ARC processor의 모든 hardware 기능을 지원하지 않습니다. 자세한 내용은 ARC QEMU 문서를 확인해야 합니다.
- Single-thread kernel은 single-core target에서만 지원됩니다.
- 현재 ARC VPX scalar port만 지원합니다. VPX vector pipeline, VCCM, STU 지원은 이 port에 포함되지 않았으며 추가 개발 또는 다른 runtime integration이 필요합니다.
Source
출처
영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.