Renesas SmartBond NOR/PSRAM 바인딩

:orphan:

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.. dtcompatible:: renesas,smartbond-nor-psram
.. _dtbinding_renesas_smartbond_nor_psram:

renesas,smartbond-nor-psram
###########################

Vendor: :ref:`Renesas Electronics Corporation <dt_vendor_renesas>`

Description
***********



.. code-block:: none

   Renesas Smartbond(tm) NOR/PSRAM controller

Properties
**********

.. tabs::

   .. group-tab:: Node specific properties

      Properties not inherited from the base binding file.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``is-ram``
           - ``boolean``
           - .. code-block:: none

                If present, the memory controller will be configured to drive PSRAM devices.



         * - ``dev-size``
           - ``int``
           - .. code-block:: none

                Memory size/capacity in bits.



             This property is **required**.

         * - ``dev-type``
           - ``int``
           - .. code-block:: none

                Device type, part of device ID, used to verify the memory device used.



             This property is **required**.

         * - ``dev-density``
           - ``int``
           - .. code-block:: none

                Device density, part of device ID, used to verify the memory device used.
                [7:0] should reflect the density value itself and [15:8] should reflect
                the mask that should be applied to the returned device ID value.
                This is because part of its byte value might contain invalid bits.



             This property is **required**.

         * - ``dev-id``
           - ``int``
           - .. code-block:: none

                Manufacturer ID, part of device ID, used to verify the memory device used.



             This property is **required**.

         * - ``reset-delay-us``
           - ``int``
           - .. code-block:: none

                Time in microseconds (us) the memory device can accept the next command following a SW reset.



             This property is **required**.

         * - ``read-cs-idle-min-ns``
           - ``int``
           - .. code-block:: none

                Min. time, in nanoseconds, the #CS line should remain inactive between
                the transmission of two different instructions.



             This property is **required**.

         * - ``erase-cs-idle-min-ns``
           - ``int``
           - .. code-block:: none

                Min. time, in nanoseconds, the #CS line should remain inactive after the execution
                of a write enable, erase, erase suspend or erase resume instruction. This setting
                is not used if is-ram property is present.



         * - ``enter-qpi-cmd``
           - ``int``
           - .. code-block:: none

                Command to enter the QPI mode supported by a memory device
                (should be transmitted in single bus mode).



         * - ``exit-qpi-cmd``
           - ``int``
           - .. code-block:: none

                Command to exit the QPI mode supported by a memory device
                (should be transmitted in quad bus mode).



         * - ``enter-qpi-mode``
           - ``boolean``
           - .. code-block:: none

                If present, the memory device will enter the QPI mode which typically reflects that
                all bytes be sent in quad bus mode. It's a pre-requisite that read and write
                commands, that should be read-cmd and write-cmd respectively, reflect the QPI mode.



         * - ``read-cmd``
           - ``int``
           - .. code-block:: none

                Read command for single/burst read accesses in auto mode. Default value is the opcode
                for single mode which is supported by all memory devices.



             Default value: ``3``

         * - ``write-cmd``
           - ``int``
           - .. code-block:: none

                Write command for single/burst write accesses in auto mode. Default value is the opcode
                for single mode which is supported by all memory devices.



             Default value: ``2``

         * - ``clock-mode``
           - ``string``
           - .. code-block:: none

                Clock mode when #CS is idle/inactive

                - Mode0: #CLK is low when #CS is inactive
                - Mode3: #CLK is high when #CS is inactive

                Mode0 is selected by default as it should be supported by all memory devices.



             Default value: ``spi-mode0``

             Legal values: ``'spi-mode0'``, ``'spi-mode3'``

         * - ``addr-range``
           - ``string``
           - .. code-block:: none

                Address size to use in auto mode. In 24-bit mode up to 16MB can be
                accessed whilst in 32-bit mode up to 32MB can be accessed which is
                the max. address space supported by QSPICx. Default value is 24-bit
                mode which is supported by all memory devices.



             Default value: ``addr-range-24bit``

             Legal values: ``'addr-range-24bit'``, ``'addr-range-32bit'``

         * - ``clock-div``
           - ``int``
           - .. code-block:: none

                Clock divider for QSPIC2 controller. The clock path of
                this block is always DIV1 which reflects the current
                system clock.



         * - ``tcem-max-us``
           - ``int``
           - .. code-block:: none

                If a non zero value is applied, then Tcem should be taken into
                consideration by QSPIC2 so that it can split a burst read/write
                access in case the total time exceeds the defined value
                (at the cost of extra cycles required for re-sending the instruction,
                address and dummy bytes, if any). This setting is meaningful only if
                is-ram is present. This value reflects the max. time in microseconds
                the #CS line can be driven low in a write/read burst access
                (required for the auto-refresh mechanism, when supported).



         * - ``dummy-bytes-count``
           - ``string``
           - .. code-block:: none

                Number of dummy bytes to send for single/burst read access in auto mode.



             This property is **required**.

             Legal values: ``'dummy-bytes-count0'``, ``'dummy-bytes-count1'``, ``'dummy-bytes-count2'``, ``'dummy-bytes-count4'``

         * - ``extra-byte-enable``
           - ``boolean``
           - .. code-block:: none

                If present, the extra byte will be sent after the dummy bytes, if any.
                This should be useful if 3 dummy bytes are required. In such a case,
                dummy-bytes-count should be set to 2.



         * - ``extra-byte``
           - ``int``
           - .. code-block:: none

                Extra byte to be sent, if extra-byte-enable is present.



         * - ``rx-addr-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the address phase for single/burst
                read accesses in auto mode. Default value is single mode which should be
                supported by all memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``rx-inst-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the instruction phase for single/burst
                read accesses in auto mode. Default value is single mode which should be
                supported by all memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``rx-data-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the data phase for single/burst
                read accesses in auto mode. Default value is single mode which should
                be supported by all memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``rx-dummy-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the dummy bytes phase for single/burst
                read accesses in auto mode. The single mode should be supported by all
                memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``rx-extra-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the extra byte phase for single/burst
                read accesses in auto mode. Default value is single mode which should be
                supported by all memory devices.



             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``tx-addr-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the address phase for single/burst
                write accesses in auto mode. Default value is single mode which should
                be supported by all memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``tx-inst-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the instruction phase for single/burst
                write accesses in auto mode. The single mode should be supported by all
                memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``

         * - ``tx-data-mode``
           - ``string``
           - .. code-block:: none

                Describes the mode of SPI bus during the data phase for single/burst
                write accesses in auto mode. Default value is single mode which should
                be supported by all memory devices.



             Default value: ``single-spi``

             Legal values: ``'single-spi'``, ``'dual-spi'``, ``'quad-spi'``



   .. group-tab:: Deprecated node specific properties

      Deprecated properties not inherited from the base binding file.

      (None)

   .. group-tab:: Base properties

      Properties inherited from the base binding file, which defines
      common properties that may be set on many nodes. Not all of these
      may apply to the "renesas,smartbond-nor-psram" compatible.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``wakeup-source``
           - ``boolean``
           - .. code-block:: none

                Property to identify that a device can be used as wake up source.

                When this property is provided a specific flag is set into the
                device that tells the system that the device is capable of
                wake up the system.

                Wake up capable devices are disabled (interruptions will not wake up
                the system) by default but they can be enabled at runtime if necessary.



         * - ``power-domain``
           - ``phandle``
           - .. code-block:: none


                Power domain the device belongs to.

                The device will be notified when the power domain it belongs to is either
                suspended or resumed.



         * - ``zephyr,pm-device-runtime-auto``
           - ``boolean``
           - .. code-block:: none

                Automatically configure the device for runtime power management after the
                init function runs.



         * - ``zephyr,disabling-power-states``
           - ``phandles``
           - .. code-block:: none

                List of power states that will disable this device power.



         * - ``status``
           - ``string``
           - .. code-block:: none

                indicates the operational status of a device


             Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``

             See :ref:`dt-important-props` for more information.

         * - ``compatible``
           - ``string-array``
           - .. code-block:: none

                compatible strings


             This property is **required**.

             See :ref:`dt-important-props` for more information.

         * - ``reg``
           - ``array``
           - .. code-block:: none

                register space


             This property is **required**.

             See :ref:`dt-important-props` for more information.

         * - ``reg-names``
           - ``string-array``
           - .. code-block:: none

                name of each register space


         * - ``interrupts``
           - ``array``
           - .. code-block:: none

                interrupts for device


             See :ref:`dt-important-props` for more information.

         * - ``interrupts-extended``
           - ``compound``
           - .. code-block:: none

                extended interrupt specifier for device


         * - ``interrupt-names``
           - ``string-array``
           - .. code-block:: none

                name of each interrupt


         * - ``interrupt-parent``
           - ``phandle``
           - .. code-block:: none

                phandle to interrupt controller node


         * - ``label``
           - ``string``
           - .. code-block:: none

                Human readable string describing the device (used as device_get_binding() argument)



             See :ref:`dt-important-props` for more information.

             This property is **deprecated**.

         * - ``clocks``
           - ``phandle-array``
           - .. code-block:: none

                Clock gate information


         * - ``clock-names``
           - ``string-array``
           - .. code-block:: none

                name of each clock


         * - ``#address-cells``
           - ``int``
           - .. code-block:: none

                number of address cells in reg property


         * - ``#size-cells``
           - ``int``
           - .. code-block:: none

                number of size cells in reg property


         * - ``dmas``
           - ``phandle-array``
           - .. code-block:: none

                DMA channels specifiers


         * - ``dma-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of DMA channel specifiers


         * - ``io-channels``
           - ``phandle-array``
           - .. code-block:: none

                IO channels specifiers


         * - ``io-channel-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of IO channel specifiers


         * - ``mboxes``
           - ``phandle-array``
           - .. code-block:: none

                mailbox / IPM channels specifiers


         * - ``mbox-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of mailbox / IPM channel specifiers


         * - ``zephyr,deferred-init``
           - ``boolean``
           - .. code-block:: none

                Do not initialize device automatically on boot. Device should be manually
                initialized using device_init().