build/dts/api/bindings/interrupt-controller/cypress,psoc6-intmux.html · build/dts/api/bindings/interrupt-controller/cypress,psoc6-intmux.rst 공식 원문 ↗

Zephyr 3.7.0 · Devicetree · Interrupt Controller · Cypress Semiconductor Corporation

Cypress PSoC6 Interrupt Multiplexer 바인딩

PSoC6 Cortex-M0+용 32-channel interrupt source multiplexer를 정의하는 24개 property schema입니다.

Official pathbuild/dts/api/bindings/interrupt-controller/cypress,psoc6-intmux.html
Source filebuild/dts/api/bindings/interrupt-controller/cypress,psoc6-intmux.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

공식 원문 322줄과 property 24행을 전수 대조해 240-to-32 source routing·8 registers × 4 channels·interrupt-parent ordering 제약을 보존했습니다.

Compatible

cypress,psoc6-intmux

Vendor

Cypress Semiconductor Corporation

Properties

24 rows

Interface

240 peripheral vectors → 32 Cortex-M0+ NVIC lines

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 173958327DAB34484AE8D202C53050263EADBED103410D7102416B1851C0AB96
:orphan:

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.. dtcompatible:: cypress,psoc6-intmux
.. _dtbinding_cypress_psoc6_intmux:

cypress,psoc6-intmux
####################

Vendor: :ref:`Cypress Semiconductor Corporation <dt_vendor_cypress>`

Description
***********



.. code-block:: none

   Cypress Interrupt Multiplex

   The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
   user can select up to 32 interrupts sources from the 240 possible vectors
   to be processed in the Cortex-M0+ CPU.

   At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
   configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
   4 interrupt sources by grouping intmux channels. These means that each byte
   from intmux[0~7] store a 'vector number' which selects the peripheral
   interrupt source in the multiplexer. The multiplexer is placed before
   Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
   directly connected to NVIC and doesn't require any special configuration.

   On a general view, the below represents the Interrupt Multiplexer
   configuration and how the Cortex-M0+ NVIC sources are organized. Each
   channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
   The vector number selects the PSoC-6 peripheral interrupt source for the
   Cortex-M0+ NVIC controller line.

   intmux[0] = {ch03, ch02, ch01, ch00}
   intmux[1] = {ch07, ch06, ch05, ch04}
   ...
   intmux[7] = {ch31, ch30, ch29, ch28}

   In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
   sources and the proper NVIC interrupt order. With that, the system configures
   the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
   More information about it at PSoC-6 Architecture Technical Reference Manual,
   section CPU Sub System (CPUSS) Registers.


   The below fragment configure the GPIO Port 0 to generate an interrupt at
   Cortex-M0+ NVIC:

   At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:

   gpio_prt0: gpio@40320100 {
     interrupts = <2 1>;
   };

   In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
   must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
   This can be defined at <board>_m0.dts file:

   &gpio_prt0 {
     interrupt-parent = <&intmux_ch20>;
   };

   The translation of these two definitions is:
          CH   REGS  INT NUM    CH   CH/REG
   intmux[20 mod 8] |= 0x02 << (20 mod 4);

   These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2.
   The interrupt can be enabled/disabled at NVIC at line 20 as usual.

   Notes:
   1) Multiple definitions will generate multiple interrupts
   2) The interrupt sources are shared between Cortex-M0+/M4. This means, they
      can trigger actions in parallel on both processors.
   3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
      at interrupt-parent properties.
   4) Only the peripherals used by Cortex-M0+ should be configured.

Properties
**********

.. tabs::

   .. group-tab:: Node specific properties

      Properties not inherited from the base binding file.

      (None)

   .. group-tab:: Deprecated node specific properties

      Deprecated properties not inherited from the base binding file.

      (None)

   .. group-tab:: Base properties

      Properties inherited from the base binding file, which defines
      common properties that may be set on many nodes. Not all of these
      may apply to the "cypress,psoc6-intmux" compatible.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``wakeup-source``
           - ``boolean``
           - .. code-block:: none

                Property to identify that a device can be used as wake up source.

                When this property is provided a specific flag is set into the
                device that tells the system that the device is capable of
                wake up the system.

                Wake up capable devices are disabled (interruptions will not wake up
                the system) by default but they can be enabled at runtime if necessary.



         * - ``power-domain``
           - ``phandle``
           - .. code-block:: none


                Power domain the device belongs to.

                The device will be notified when the power domain it belongs to is either
                suspended or resumed.



         * - ``zephyr,pm-device-runtime-auto``
           - ``boolean``
           - .. code-block:: none

                Automatically configure the device for runtime power management after the
                init function runs.



         * - ``zephyr,disabling-power-states``
           - ``phandles``
           - .. code-block:: none

                List of power states that will disable this device power.



         * - ``status``
           - ``string``
           - .. code-block:: none

                indicates the operational status of a device


             Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``

             See :ref:`dt-important-props` for more information.

         * - ``compatible``
           - ``string-array``
           - .. code-block:: none

                compatible strings


             This property is **required**.

             See :ref:`dt-important-props` for more information.

         * - ``reg``
           - ``array``
           - .. code-block:: none

                register space


             This property is **required**.

             See :ref:`dt-important-props` for more information.

         * - ``reg-names``
           - ``string-array``
           - .. code-block:: none

                name of each register space


         * - ``interrupts``
           - ``array``
           - .. code-block:: none

                interrupts for device


             See :ref:`dt-important-props` for more information.

         * - ``interrupts-extended``
           - ``compound``
           - .. code-block:: none

                extended interrupt specifier for device


         * - ``interrupt-names``
           - ``string-array``
           - .. code-block:: none

                name of each interrupt


         * - ``interrupt-parent``
           - ``phandle``
           - .. code-block:: none

                phandle to interrupt controller node


         * - ``label``
           - ``string``
           - .. code-block:: none

                Human readable string describing the device (used as device_get_binding() argument)



             See :ref:`dt-important-props` for more information.

             This property is **deprecated**.

         * - ``clocks``
           - ``phandle-array``
           - .. code-block:: none

                Clock gate information


         * - ``clock-names``
           - ``string-array``
           - .. code-block:: none

                name of each clock


         * - ``#address-cells``
           - ``int``
           - .. code-block:: none

                number of address cells in reg property


         * - ``#size-cells``
           - ``int``
           - .. code-block:: none

                number of size cells in reg property


         * - ``dmas``
           - ``phandle-array``
           - .. code-block:: none

                DMA channels specifiers


         * - ``dma-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of DMA channel specifiers


         * - ``io-channels``
           - ``phandle-array``
           - .. code-block:: none

                IO channels specifiers


         * - ``io-channel-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of IO channel specifiers


         * - ``mboxes``
           - ``phandle-array``
           - .. code-block:: none

                mailbox / IPM channels specifiers


         * - ``mbox-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of mailbox / IPM channel specifiers


         * - ``zephyr,deferred-init``
           - ``boolean``
           - .. code-block:: none

                Do not initialize device automatically on boot. Device should be manually
                initialized using device_init().






Part 3

한국어 전문 번역

cypress,psoc6-intmux

Vendor: Cypress Semiconductor Corporation

공식 설명

Cypress Interrupt Multiplex

The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
user can select up to 32 interrupts sources from the 240 possible vectors
to be processed in the Cortex-M0+ CPU.

At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
4 interrupt sources by grouping intmux channels. These means that each byte
from intmux[0~7] store a 'vector number' which selects the peripheral
interrupt source in the multiplexer. The multiplexer is placed before
Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
directly connected to NVIC and doesn't require any special configuration.

On a general view, the below represents the Interrupt Multiplexer
configuration and how the Cortex-M0+ NVIC sources are organized. Each
channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
The vector number selects the PSoC-6 peripheral interrupt source for the
Cortex-M0+ NVIC controller line.

intmux[0] = {ch03, ch02, ch01, ch00}
intmux[1] = {ch07, ch06, ch05, ch04}
...
intmux[7] = {ch31, ch30, ch29, ch28}

In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
sources and the proper NVIC interrupt order. With that, the system configures
the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
More information about it at PSoC-6 Architecture Technical Reference Manual,
section CPU Sub System (CPUSS) Registers.


The below fragment configure the GPIO Port 0 to generate an interrupt at
Cortex-M0+ NVIC:

At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:

gpio_prt0: gpio@40320100 {
  interrupts = <2 1>;
};

In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
This can be defined at <board>_m0.dts file:

&gpio_prt0 {
  interrupt-parent = <&intmux_ch20>;
};

The translation of these two definitions is:
       CH   REGS  INT NUM    CH   CH/REG
intmux[20 mod 8] |= 0x02 << (20 mod 4);

These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2.
The interrupt can be enabled/disabled at NVIC at line 20 as usual.

Notes:
1) Multiple definitions will generate multiple interrupts
2) The interrupt sources are shared between Cortex-M0+/M4. This means, they
   can trigger actions in parallel on both processors.
3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
   at interrupt-parent properties.
4) Only the peripherals used by Cortex-M0+ should be configured.

PSoC6 Cortex-M0+ Interrupt Multiplexer

Cortex-M0+ NVIC는 최대 32 interrupt를 처리하므로 240개 가능한 peripheral vector 중 최대 32개 source를 선택합니다. CPUSS의 intmux[0..7] register 8개가 각각 channel 4개를 담당하며 각 byte에 선택할 vector number를 저장합니다.

PSoC6 INTMUX channel layout
240 peripheral sources

vector number 0~239

INTMUX registers

intmux[0..7] · register당 4 channel

32 channel bytes

ch00~ch31 · byte마다 vector 선택

Cortex-M0+ NVIC

line 0~31

공식 예는 GPIO Port 0 source 2를 interrupt-parent = <&intmux_ch20>에 연결합니다. 계산은 intmux[20 mod 8] |= 0x02 << (20 mod 4)이며 결과적으로 Cortex-M0+ NVIC line 20이 source 2를 처리합니다.

Cortex-M4는 모든 source가 NVIC에 직접 연결되어 이 설정이 필요 없습니다. Source는 M0+/M4 사이에 공유되어 두 processor에서 병렬 action을 일으킬 수 있고, channel 선택으로 M0+ priority order를 바꿀 수 있습니다.

Parent 자체에는 node-specific property가 없고 base compatible·reg만 필수입니다.

속성 전체 번역

Node-specific 항목 없이 공식 base 24개 property를 모두 번역했습니다.

Base binding property · 24개

공통 기본 바인딩에서 상속한 속성입니다. 이 compatible에서 사용하지 않는 속성도 공식 참조 문서에 실려 있으면 함께 표시합니다.

이름형식설명과 제약
wakeup-sourceboolean이 장치를 시스템 깨우기에 사용할 수 있음을 나타냅니다. 이 속성이 있으면 깨우기 지원 플래그가 설정됩니다. 기본 상태에서는 장치의 인터럽트로 시스템을 깨우지 않으며, 실행 중에 깨우기 기능을 활성화할 수 있습니다.
power-domainphandle장치가 속한 전원 도메인의 phandle입니다. 해당 전원 도메인이 일시 중단되거나 다시 동작하면 장치에 알림이 전달됩니다.
zephyr,pm-device-runtime-autoboolean초기화 함수 실행 후 장치의 런타임 전원 관리를 자동으로 설정합니다.
zephyr,disabling-power-statesphandles이 장치의 전원이 꺼지는 전원 상태 목록입니다.
statusstring장치의 동작 상태를 나타냅니다.
허용값: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss'
compatiblestring-array이 노드에 적용할 바인딩과 드라이버를 식별하는 compatible 문자열 목록입니다.
필수
regarray장치 레지스터의 주소 범위를 지정합니다.
필수
reg-namesstring-array각 register space의 이름입니다.
interruptsarray장치에서 사용하는 인터럽트를 지정하는 목록입니다.
interrupts-extendedcompound인터럽트 컨트롤러의 phandle을 함께 지정하는 확장 형식의 인터럽트 명세입니다.
interrupt-namesstring-array각 interrupt의 이름입니다.
interrupt-parentphandle인터럽트 컨트롤러 노드를 가리키는 phandle입니다.
labelstring사람이 장치를 알아볼 수 있도록 붙이는 이름입니다. 과거에는 device_get_binding()의 인자로 사용했습니다.
사용 중단됨
clocksphandle-array클록 게이트 또는 클록 공급원을 지정하는 phandle 배열입니다.
clock-namesstring-array각 clock의 이름입니다.
#address-cellsint하위 노드의 reg 속성에서 주소를 나타내는 데 쓰는 셀 수입니다.
#size-cellsint하위 노드의 reg 속성에서 크기를 나타내는 데 쓰는 셀 수입니다.
dmasphandle-arrayDMA 채널을 지정하는 phandle 배열입니다.
dma-namesstring-array지정한 DMA 채널의 이름입니다.
io-channelsphandle-arrayI/O 채널을 지정하는 phandle 배열입니다.
io-channel-namesstring-array지정한 I/O 채널의 이름입니다.
mboxesphandle-array메일박스/IPM 채널을 지정하는 phandle 배열입니다.
mbox-namesstring-array지정한 메일박스/IPM 채널의 이름입니다.
zephyr,deferred-initboolean부팅할 때 장치를 자동으로 초기화하지 않습니다. 이후 device_init()를 호출해 직접 초기화해야 합니다.

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