Zephyr panel timing binding 한국어 번역

Part 1

요약·해설

공식 원문 223줄과 property 12행을 전수 대조해 geometry·timing·bus·initialization register 제약을 보존했습니다.

Compatible

zephyr,panel-timing

Vendor

Zephyr-specific binding

Properties

12 rows

Interface

Parallel RGB timing

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기

원문 SHA-256 F85E6D037E1EBA7A3417D7337232CC6F3E010CD7EAEA5876A4A4B085949A996B

:orphan:

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.. dtcompatible:: zephyr,panel-timing
.. _dtbinding_panel_timing:

zephyr,panel-timing
###################

Vendor: :ref:`Zephyr-specific binding <dt_vendor_zephyr>`

Description
***********



.. code-block:: none

   Common timing settings for display panels. These timings can be added to
   a panel under display-timings node. For example:

   &lcdif {
     display-timings {
       compatible = "zephyr,panel-timing";
       hsync-len = <8>;
       hfront-porch = <32>;
       hback-porch = <32>;
       vsync-len = <2>;
       vfront-porch = <16>;
       vback-porch = <14>;
       hsync-active = <0>;
       vsync-active = <0>;
       de-active = <1>;
       pixelclk-active = <0>;
       clock-frequency = <62346240>;
     };
   };

Properties
**********

.. tabs::

   .. group-tab:: Node specific properties

      Properties not inherited from the base binding file.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``clock-frequency``
           - ``int``
           - .. code-block:: none

                Pixel clock for display controller in Hz. Must be at least as large as:
                (height + vsync-len + vfront-porch + vback-porch) *
                (width + hsync-len + hfront-porch + hback-porch) *
                desired frame rate



         * - ``hsync-len``
           - ``int``
           - .. code-block:: none

                Horizontal synchronization pulse duration of panel driven by this
                controller, in pixels



             This property is **required**.

         * - ``vsync-len``
           - ``int``
           - .. code-block:: none

                Vertical synchronization pulse duration of panel driven by this
                controller, in lines



             This property is **required**.

         * - ``hback-porch``
           - ``int``
           - .. code-block:: none

                Horizontal back porch duration of panel driven by this controller,
                in pixels



             This property is **required**.

         * - ``vback-porch``
           - ``int``
           - .. code-block:: none

                Vertical back porch duration of panel driven by this controller, in lines



             This property is **required**.

         * - ``hfront-porch``
           - ``int``
           - .. code-block:: none

                Horizontal front porch duration of panel driven by this controller,
                in pixels



             This property is **required**.

         * - ``vfront-porch``
           - ``int``
           - .. code-block:: none

                Vertical front porch duration of panel driven by this controller, in lines



             This property is **required**.

         * - ``hsync-active``
           - ``int``
           - .. code-block:: none

                Polarity of horizontal sync pulse
                0 selects active low
                1 selects active high



             This property is **required**.

             Legal values: ``0``, ``1``

         * - ``vsync-active``
           - ``int``
           - .. code-block:: none

                Polarity of vertical sync pulse
                0 selects active low
                1 selects active high



             This property is **required**.

             Legal values: ``0``, ``1``

         * - ``de-active``
           - ``int``
           - .. code-block:: none

                Polarity of data enable, sent with each horizontal interval.
                0 selects active low
                1 selects active high.



             This property is **required**.

             Legal values: ``0``, ``1``

         * - ``pixelclk-active``
           - ``int``
           - .. code-block:: none

                Polarity of pixel clock. Selects which edge to drive data to display on.
                0 drives pixel data on falling edge, and samples on rising edge.
                1 drives pixel data on rising edge, and samples data on falling edge



             This property is **required**.

             Legal values: ``0``, ``1``

         * - ``syncclk-active``
           - ``int``
           - .. code-block:: none

                Drive sync on rising or sample sync on falling edge. If not specified
                then the controller uses the setup specified by pixelclk-active.
                Use 0 to drive sync on falling edge
                and sample sync on rising edge of pixel clock.
                Use 1 to drive sync on rising edge
                and sample sync on falling edge of pixel clock.



             Legal values: ``0``, ``1``



   .. group-tab:: Deprecated node specific properties

      Deprecated properties not inherited from the base binding file.

      (None)

   .. group-tab:: Base properties

      Properties inherited from the base binding file, which defines
      common properties that may be set on many nodes. Not all of these
      may apply to the "zephyr,panel-timing" compatible.

      (None)

Part 3

한국어 전문 번역

`zephyr,panel-timing`

Vendor: Zephyr-specific binding

공식 설명

Common timing settings for display panels. These timings can be added to
a panel under display-timings node. For example:

&lcdif {
  display-timings {
    compatible = "zephyr,panel-timing";
    hsync-len = <8>;
    hfront-porch = <32>;
    hback-porch = <32>;
    vsync-len = <2>;
    vfront-porch = <16>;
    vback-porch = <14>;
    hsync-active = <0>;
    vsync-active = <0>;
    de-active = <1>;
    pixelclk-active = <0>;
    clock-frequency = <62346240>;
  };
};

한 frame을 구성하는 timing

horizontal line
[ HSYNC ][ back porch ][ active width ][ front porch ]

vertical frame
[ VSYNC ][ back porch ][ active height ][ front porch ]

hsync-len·hback-porch·hfront-porch는 pixel clock 단위이고, vertical 세 값은 line 단위입니다. 네 polarity 값은 0 또는 1이며 syncclk-active를 생략하면 pixelclk-active edge 설정을 따릅니다.

필요한 최소 pixel clock은 (height + vsync + vfront + vback) × (width + hsync + hfront + hback) × frame rate입니다. 공식 DTS 예제를 아래 원문과 함께 보존했습니다.

속성 전체 번역

공식 Zephyr 3.7.0 schema의 모든 property를 옮겼습니다. Type, required·deprecated, constant·default·legal value와 initialization byte 배열은 원문에서 직접 추출했습니다.

노드 전용 속성 · 12개

이름	형식	설명과 제약
`clock-frequency`	`int`	Display controller의 pixel clock 주파수이며 Hz 단위입니다. 전체 horizontal·vertical timing과 목표 frame rate의 곱 이상이어야 합니다.
`hsync-len`	`int`	Horizontal synchronization pulse 길이이며 pixel clock 단위입니다. 필수
`vsync-len`	`int`	Vertical synchronization pulse 길이이며 line 단위입니다. 필수
`hback-porch`	`int`	Horizontal back porch 길이이며 pixel clock 단위입니다. 필수
`vback-porch`	`int`	Vertical back porch 길이이며 line 단위입니다. 필수
`hfront-porch`	`int`	Horizontal front porch 길이이며 pixel clock 단위입니다. 필수
`vfront-porch`	`int`	Vertical front porch 길이이며 line 단위입니다. 필수
`hsync-active`	`int`	HSYNC pulse polarity입니다. 0은 active-low, 1은 active-high입니다. 필수 · 허용값: `0`, `1`
`vsync-active`	`int`	VSYNC pulse polarity입니다. 0은 active-low, 1은 active-high입니다. 필수 · 허용값: `0`, `1`
`de-active`	`int`	각 horizontal interval과 함께 전달되는 data-enable polarity입니다. 0은 active-low, 1은 active-high입니다. 필수 · 허용값: `0`, `1`
`pixelclk-active`	`int`	Pixel data를 구동하고 sample할 clock edge를 선택합니다. 0은 falling edge 구동·rising edge sample, 1은 그 반대입니다. 필수 · 허용값: `0`, `1`
`syncclk-active`	`int`	Sync 신호를 구동하고 sample할 pixel-clock edge를 선택합니다. 생략하면 pixelclk-active 설정을 따릅니다. 허용값: `0`, `1`

Source

출처

영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.

Zephyr panel timing binding

2.7.0 LTS2 · 준비 중