Part 1
요약·해설
공식 원문 103줄과 property 3행을 전수 대조해 Description과 type·required·constant·default·legal value를 보존했습니다.
st,stm32c0-hsi-clock
STMicroelectronics
3 rows
STM32C0 HSI48 to HSISYS
Part 2
접을 수 있는 영어 원문 전체
영어 원문 전체 펼치기
AE052F00F57DD2B225E394A093F9FF1A9203702646A65D54E4935CD28066FECF
:orphan:
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.. dtcompatible:: st,stm32c0-hsi-clock
.. _dtbinding_st_stm32c0_hsi_clock:
st,stm32c0-hsi-clock
####################
Vendor: :ref:`STMicroelectronics <dt_vendor_st>`
Description
***********
.. code-block:: none
STM32 HSI Clock node description for STM32C0 devices
On STM32C0, HSI is a 48MHz fixed clock.
It also produces a HSISYS secondary clk which can be used as system clock
source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
SYSCLK = HSI48 / HSI DIV
enum:
- 1 ==> HSISYS = 48MHZ
- 2 ==> HSISYS = 24MHZ
- 4 ==> HSISYS = 12MHZ
- 8 ==> HSISYS = 6MHZ
- 16 ==> HSISYS = 3MHZ
- 32 ==> HSISYS = 1.5MHz
- 64 ==> HSISYS = 0.75MHZ
- 128 ==> HSISYS = 0.375MHz
Properties
**********
.. tabs::
.. group-tab:: Node specific properties
Properties not inherited from the base binding file.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``#clock-cells``
- ``int``
- .. code-block:: none
Number of items to expect in a Clock specifier
This property is **required**.
* - ``clock-frequency``
- ``int``
- .. code-block:: none
output clock frequency (Hz)
This property is **required**.
* - ``hsi-div``
- ``int``
- .. code-block:: none
HSI clock divider. Configures the output HSI clock frequency (HSISYS).
This property is **required**.
Legal values: ``1``, ``2``, ``4``, ``8``, ``16``, ``32``, ``64``, ``128``
.. group-tab:: Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
.. group-tab:: Base properties
Properties inherited from the base binding file, which defines
common properties that may be set on many nodes. Not all of these
may apply to the "st,stm32c0-hsi-clock" compatible.
(None)
Part 3
한국어 전문 번역
st,stm32c0-hsi-clock
Vendor: STMicroelectronics
공식 설명
STM32 HSI Clock node description for STM32C0 devices
On STM32C0, HSI is a 48MHz fixed clock.
It also produces a HSISYS secondary clk which can be used as system clock
source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
SYSCLK = HSI48 / HSI DIV
enum:
- 1 ==> HSISYS = 48MHZ
- 2 ==> HSISYS = 24MHZ
- 4 ==> HSISYS = 12MHZ
- 8 ==> HSISYS = 6MHZ
- 16 ==> HSISYS = 3MHZ
- 32 ==> HSISYS = 1.5MHz
- 64 ==> HSISYS = 0.75MHZ
- 128 ==> HSISYS = 0.375MHzSTM32C0 48 MHz HSI와 HSISYS secondary clock divider를 정의합니다.
HSISYS 계산
SYSCLK = HSI48 / hsi-div입니다. 허용 divider 1·2·4·8·16·32·64·128은 각각 48·24·12·6·3·1.5·0.75·0.375 MHz를 만듭니다.
#clock-cells, clock-frequency, hsi-div가 모두 필수이며 base property 표는 없습니다.
Property
공식 Zephyr 3.7.0 schema의 모든 property를 옮겼습니다. Type과 required·deprecated·constant·default·legal value를 원문에서 직접 추출했습니다.
노드 전용 속성 · 3개
| 이름 | 형식 | 설명과 제약 |
|---|---|---|
#clock-cells | int | Consumer의 clock specifier에서 기대할 item 수입니다. 필수 |
clock-frequency | int | Clock output 또는 core clock frequency를 Hz 단위로 지정합니다. 필수 |
hsi-div | int | 48 MHz HSI에서 HSISYS를 만드는 divider입니다. 필수 · 허용값: 1, 2, 4, 8, 16, 32, 64, 128 |
Source
출처
영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.