Part 1
요약·해설
공식 원문 400줄과 property 30행을 전수 대조해 Description과 type·required·constant·default·legal value를 보존했습니다.
st,stm32-rcc
STMicroelectronics
30 rows
SYSCLK, gated and domain clocks
Part 2
접을 수 있는 영어 원문 전체
영어 원문 전체 펼치기
15DA2F7CDBB89275F0C07E4DE1A5AB00D185DA55558B189D8F5302DF8DD51E81
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.. dtcompatible:: st,stm32-rcc
.. _dtbinding_st_stm32_rcc:
st,stm32-rcc
############
Vendor: :ref:`STMicroelectronics <dt_vendor_st>`
Description
***********
.. code-block:: none
STM32 Reset and Clock controller node.
This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
Configuring STM32 Reset and Clock controller node:
System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_hsi', 'pll', ...).
Core clock frequency should also be defined, using "clock-frequency" property.
Note:
Core clock frequency = SYSCLK / AHB prescaler
Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
ahb-prescaler = <2>;
clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
apb1-presacler = <1>;
apb2-presacler = <1>;
}
Specifying a gated clock:
To specify a gated clock, a peripheral should define a "clocks" property encoded
in the following way:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
The gated clock is required when accessing to the peripheral controller is needed
(generally for configuring the device). If dual clock domain is not used, it is
also used for peripheral operation.
Specifying a domain clock source:
Specifying a domain source clock could be done by adding a clock specifier to the
clock property:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
...
}
In this example, I2C1 device is assigned HSI as domain clock source.
Domain clock is independent from the bus/gated clock and allows access to the device's
register while the gated clock is off. As it doesn't feed the peripheral's controller, it
allows peripheral operation, but can't be used for peripheral configuration.
It is peripheral driver's responsibility to query and use clock source information in
accordance with clock_control API specifications.
Since the peripheral subsystem rate is dictated by the clock used for peripheral
operation, same clock should be used in calls to `clock_control_get_rate()`
Note 1: No additional specifier means gating clock is also the clock source (ie
'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
cell to explicitly set it.
Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
should be the one matching SoC reset state. Confere reference manual to check
what is the reset value of the clock source for each peripheral.
Properties
**********
.. tabs::
.. group-tab:: Node specific properties
Properties not inherited from the base binding file.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``#clock-cells``
- ``int``
- .. code-block:: none
Number of items to expect in a Clock specifier
This property is **required**.
Constant value: ``2``
* - ``clock-frequency``
- ``int``
- .. code-block:: none
default frequency in Hz for clock output
This property is **required**.
* - ``ahb-prescaler``
- ``int``
- .. code-block:: none
AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.
This property is **required**.
Legal values: ``1``, ``2``, ``4``, ``8``, ``16``, ``64``, ``128``, ``256``, ``512``
* - ``apb1-prescaler``
- ``int``
- This property is **required**.
Legal values: ``1``, ``2``, ``4``, ``8``, ``16``
* - ``apb2-prescaler``
- ``int``
- This property is **required**.
Legal values: ``1``, ``2``, ``4``, ``8``, ``16``
* - ``undershoot-prevention``
- ``boolean``
- .. code-block:: none
On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.
.. group-tab:: Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
.. group-tab:: Base properties
Properties inherited from the base binding file, which defines
common properties that may be set on many nodes. Not all of these
may apply to the "st,stm32-rcc" compatible.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``wakeup-source``
- ``boolean``
- .. code-block:: none
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
* - ``power-domain``
- ``phandle``
- .. code-block:: none
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
* - ``zephyr,pm-device-runtime-auto``
- ``boolean``
- .. code-block:: none
Automatically configure the device for runtime power management after the
init function runs.
* - ``zephyr,disabling-power-states``
- ``phandles``
- .. code-block:: none
List of power states that will disable this device power.
* - ``status``
- ``string``
- .. code-block:: none
indicates the operational status of a device
Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``
See :ref:`dt-important-props` for more information.
* - ``compatible``
- ``string-array``
- .. code-block:: none
compatible strings
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``reg``
- ``array``
- .. code-block:: none
register space
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``reg-names``
- ``string-array``
- .. code-block:: none
name of each register space
* - ``interrupts``
- ``array``
- .. code-block:: none
interrupts for device
See :ref:`dt-important-props` for more information.
* - ``interrupts-extended``
- ``compound``
- .. code-block:: none
extended interrupt specifier for device
* - ``interrupt-names``
- ``string-array``
- .. code-block:: none
name of each interrupt
* - ``interrupt-parent``
- ``phandle``
- .. code-block:: none
phandle to interrupt controller node
* - ``label``
- ``string``
- .. code-block:: none
Human readable string describing the device (used as device_get_binding() argument)
See :ref:`dt-important-props` for more information.
This property is **deprecated**.
* - ``clocks``
- ``phandle-array``
- .. code-block:: none
Clock gate information
* - ``clock-names``
- ``string-array``
- .. code-block:: none
name of each clock
* - ``#address-cells``
- ``int``
- .. code-block:: none
number of address cells in reg property
* - ``#size-cells``
- ``int``
- .. code-block:: none
number of size cells in reg property
* - ``dmas``
- ``phandle-array``
- .. code-block:: none
DMA channels specifiers
* - ``dma-names``
- ``string-array``
- .. code-block:: none
Provided names of DMA channel specifiers
* - ``io-channels``
- ``phandle-array``
- .. code-block:: none
IO channels specifiers
* - ``io-channel-names``
- ``string-array``
- .. code-block:: none
Provided names of IO channel specifiers
* - ``mboxes``
- ``phandle-array``
- .. code-block:: none
mailbox / IPM channels specifiers
* - ``mbox-names``
- ``string-array``
- .. code-block:: none
Provided names of mailbox / IPM channel specifiers
* - ``zephyr,deferred-init``
- ``boolean``
- .. code-block:: none
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
Specifier cell names
********************
- clock cells: bus, bits
Part 3
한국어 전문 번역
st,stm32-rcc
Vendor: STMicroelectronics
공식 설명
STM32 Reset and Clock controller node.
This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
Configuring STM32 Reset and Clock controller node:
System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_hsi', 'pll', ...).
Core clock frequency should also be defined, using "clock-frequency" property.
Note:
Core clock frequency = SYSCLK / AHB prescaler
Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
ahb-prescaler = <2>;
clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
apb1-presacler = <1>;
apb2-presacler = <1>;
}
Specifying a gated clock:
To specify a gated clock, a peripheral should define a "clocks" property encoded
in the following way:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
The gated clock is required when accessing to the peripheral controller is needed
(generally for configuring the device). If dual clock domain is not used, it is
also used for peripheral operation.
Specifying a domain clock source:
Specifying a domain source clock could be done by adding a clock specifier to the
clock property:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
...
}
In this example, I2C1 device is assigned HSI as domain clock source.
Domain clock is independent from the bus/gated clock and allows access to the device's
register while the gated clock is off. As it doesn't feed the peripheral's controller, it
allows peripheral operation, but can't be used for peripheral configuration.
It is peripheral driver's responsibility to query and use clock source information in
accordance with clock_control API specifications.
Since the peripheral subsystem rate is dictated by the clock used for peripheral
operation, same clock should be used in calls to clock_control_get_rate()
Note 1: No additional specifier means gating clock is also the clock source (ie
'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
cell to explicitly set it.
Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
should be the one matching SoC reset state. Confere reference manual to check
what is the reset value of the clock source for each peripheral.STM32 SYSCLK source, AHB/APB prescaler, peripheral gated clock와 독립 domain clock을 정의하는 공통 RCC binding입니다.
SYSCLK에서 HCLK·PCLK로
clocks에서 HSE·HSI·PLL 같은 SYSCLK source를 선택하고 clock-frequency에 core HCLK를 적습니다. 관계는 HCLK = SYSCLK / ahb-prescaler입니다. APB1·APB2 prescaler로 peripheral bus clock을 이어서 구성합니다.
&rcc {
clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
ahb-prescaler = <2>;
clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
apb1-presacler = <1>;
apb2-presacler = <1>;
}원문 예제의 apb1-presacler·apb2-presacler 오타도 공식 설명에 그대로 보존했습니다. 실제 property 이름은 표의 apb1-prescaler·apb2-prescaler입니다.
Gated clock
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}두 cell은 bus register selector와 clock enable bits입니다. Gated clock은 peripheral register 접근·configuration에 필요하고, dual clock domain을 쓰지 않으면 operation clock 역할도 합니다.
독립 domain source
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
...
}두 번째 specifier는 I2C1에 HSI domain source를 지정합니다. Domain clock은 bus/gated clock과 독립이며 peripheral operation에 쓰지만 configuration에는 gated clock이 필요합니다. Driver는 실제 operation clock으로 clock_control_get_rate()를 호출해야 합니다.
추가 specifier가 없으면 PCLK/PCLK1/PCLK2 gating clock이 source도 겸합니다. DTSI 기본 clock은 SoC reset state와 맞아야 합니다.
Prescaler 제약
AHB는 1·2·4·8·16·64·128·256·512, APB1/2는 1·2·4·8·16만 허용합니다. undershoot-prevention은 일부 part에서 80 MHz 초과 전환을 중간 AHB prescaler 두 단계로 수행합니다.
Property
공식 Zephyr 3.7.0 schema의 모든 property를 옮겼습니다. Type과 required·deprecated·constant·default·legal value를 원문에서 직접 추출했습니다.
노드 전용 속성 · 6개
| 이름 | 형식 | 설명과 제약 |
|---|---|---|
#clock-cells | int | Consumer의 clock specifier에서 기대할 item 수입니다. 필수 · 고정값: 2 |
clock-frequency | int | Clock output 또는 core clock frequency를 Hz 단위로 지정합니다. 필수 |
ahb-prescaler | int | SYSCLK를 나눠 CPU·AHB·memory·DMA를 구동하는 HCLK를 만드는 prescaler입니다. 필수 · 허용값: 1, 2, 4, 8, 16, 64, 128, 256, 512 |
apb1-prescaler | int | HCLK에서 APB1 peripheral bus clock을 만드는 prescaler입니다. 필수 · 허용값: 1, 2, 4, 8, 16 |
apb2-prescaler | int | HCLK에서 APB2 peripheral bus clock을 만드는 prescaler입니다. 필수 · 허용값: 1, 2, 4, 8, 16 |
undershoot-prevention | boolean | 80 MHz를 넘는 높은 core frequency 전환 때 intermediate AHB prescaler를 적용해 undershoot를 방지합니다. |
Base binding property · 24개
공식 문서의 기본 속성을 빠짐없이 실었습니다.
| 이름 | 형식 | 설명과 제약 |
|---|---|---|
wakeup-source | boolean | 이 장치를 시스템 깨우기에 사용할 수 있음을 나타냅니다. 이 속성이 있으면 깨우기 지원 플래그가 설정됩니다. 기본 상태에서는 장치의 인터럽트로 시스템을 깨우지 않으며, 실행 중에 깨우기 기능을 활성화할 수 있습니다. |
power-domain | phandle | 장치가 속한 전원 도메인의 phandle입니다. 해당 전원 도메인이 일시 중단되거나 다시 동작하면 장치에 알림이 전달됩니다. |
zephyr,pm-device-runtime-auto | boolean | 초기화 함수 실행 후 장치의 런타임 전원 관리를 자동으로 설정합니다. |
zephyr,disabling-power-states | phandles | 이 장치의 전원이 꺼지는 전원 상태 목록입니다. |
status | string | 장치의 동작 상태를 나타냅니다. 허용값: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss' |
compatible | string-array | 이 노드에 적용할 바인딩과 드라이버를 식별하는 compatible 문자열 목록입니다. 필수 |
reg | array | 장치 레지스터의 주소 범위를 지정합니다. 필수 |
reg-names | string-array | 각 register space의 이름입니다. |
interrupts | array | 장치에서 사용하는 인터럽트를 지정하는 목록입니다. |
interrupts-extended | compound | 인터럽트 컨트롤러의 phandle을 함께 지정하는 확장 형식의 인터럽트 명세입니다. |
interrupt-names | string-array | 각 interrupt의 이름입니다. |
interrupt-parent | phandle | 인터럽트 컨트롤러 노드를 가리키는 phandle입니다. |
label | string | 사람이 장치를 알아볼 수 있도록 붙이는 이름입니다. 과거에는 device_get_binding()의 인자로 사용했습니다. 사용 중단됨 |
clocks | phandle-array | 클록 게이트 또는 클록 공급원을 지정하는 phandle 배열입니다. |
clock-names | string-array | 각 clock의 이름입니다. |
#address-cells | int | 하위 노드의 reg 속성에서 주소를 나타내는 데 쓰는 셀 수입니다. |
#size-cells | int | 하위 노드의 reg 속성에서 크기를 나타내는 데 쓰는 셀 수입니다. |
dmas | phandle-array | DMA 채널을 지정하는 phandle 배열입니다. |
dma-names | string-array | 지정한 DMA 채널의 이름입니다. |
io-channels | phandle-array | I/O 채널을 지정하는 phandle 배열입니다. |
io-channel-names | string-array | 지정한 I/O 채널의 이름입니다. |
mboxes | phandle-array | 메일박스/IPM 채널을 지정하는 phandle 배열입니다. |
mbox-names | string-array | 지정한 메일박스/IPM 채널의 이름입니다. |
zephyr,deferred-init | boolean | 부팅할 때 장치를 자동으로 초기화하지 않습니다. 이후 device_init()를 호출해 직접 초기화해야 합니다. |
지정자 셀 이름
Clock specifier cell은 bus, bits 순서입니다.
Source
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