build/dts/api/bindings/clock/nuvoton,npcx-pcc.html · build/dts/api/bindings/clock/nuvoton,npcx-pcc.rst 공식 원문 ↗

Zephyr 3.7.0 · Devicetree · Clock · Nuvoton Technology Corporation

Nuvoton NPCX PCC clock binding

33개 property로 NPCX OFMCLK and APB prescalers schema를 정의합니다.

Official pathbuild/dts/api/bindings/clock/nuvoton,npcx-pcc.html
Source filebuild/dts/api/bindings/clock/nuvoton,npcx-pcc.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

공식 원문 473줄과 property 33행을 전수 대조해 Description과 type·required·constant·default·legal value를 보존했습니다.

Compatible

nuvoton,npcx-pcc

Vendor

Nuvoton Technology Corporation

Properties

33 rows

Schema

NPCX OFMCLK and APB prescalers

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 E485FE2FDCCE11321AF8DAF2DC37F1B2EA1EDA493EA01C0BEE9EAB05F1EB09B3 
:orphan:

.. raw:: html

    <!--
    FIXME: do not limit page width until content uses another representation
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.. dtcompatible:: nuvoton,npcx-pcc
.. _dtbinding_nuvoton_npcx_pcc:

nuvoton,npcx-pcc
################

Vendor: :ref:`Nuvoton Technology Corporation <dt_vendor_nuvoton>`

Description
***********



.. code-block:: none

   Nuvoton, NPCX PCC (Power and Clock Controller) node.
   Besides power management, this node is also in charge of configuring the
   Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
   High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
   and most of NPCX hardware modules.

   Here is an example of configuring OFMCLK and the other clock sources derived
   from it in board dts file.
   &pcc {
       clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
       core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
       apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
       apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
       apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
   };

Properties
**********

.. tabs::

   .. group-tab:: Node specific properties

      Properties not inherited from the base binding file.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``#clock-cells``
           - ``int``
           - .. code-block:: none

                Number of items to expect in a Clock specifier


             This property is **required**.

         * - ``clock-frequency``
           - ``int``
           - .. code-block:: none

                Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
                only the following values are allowed:
                  120000000, 120 MHz
                  100000000, 100 MHz
                  96000000, 96 MHz
                  90000000, 90 MHz
                  80000000, 80 MHz
                  66000000, 66 MHz
                  50000000, 50 MHz
                  48000000, 48 MHz



             This property is **required**.

             Legal values: ``120000000``, ``100000000``, ``96000000``, ``90000000``, ``80000000``, ``66000000``, ``50000000``, ``48000000``

         * - ``core-prescaler``
           - ``int``
           - .. code-block:: none

                Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
                dividing OFMCLK(MCLK) and needs to meet the following requirements.
                - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
                = Only the following values are allowed:
                  1, CORE_CLK = OFMCLK
                  2, CORE_CLK = OFMCLK / 2
                  3, CORE_CLK = OFMCLK / 3
                  4, CORE_CLK = OFMCLK / 4
                  5, CORE_CLK = OFMCLK / 5
                  6, CORE_CLK = OFMCLK / 6
                  7, CORE_CLK = OFMCLK / 7
                  8, CORE_CLK = OFMCLK / 8
                  9, CORE_CLK = OFMCLK / 9
                  10, CORE_CLK = OFMCLK / 10



             This property is **required**.

             Legal values: ``1``, ``2``, ``3``, ``4``, ``5``, ``6``, ``7``, ``8``, ``9``, ``10``

         * - ``apb1-prescaler``
           - ``int``
           - .. code-block:: none

                APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
                OFMCLK(MCLK) and needs to meet the following requirements.
                - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
                - APB1_CLK must be an integer division (including 1) of CORE_CLK.
                = Only the following values are allowed:
                  1, APB1_CLK = OFMCLK
                  2, APB1_CLK = OFMCLK / 2
                  3, APB1_CLK = OFMCLK / 3
                  4, APB1_CLK = OFMCLK / 4
                  5, APB1_CLK = OFMCLK / 5
                  6, APB1_CLK = OFMCLK / 6
                  7, APB1_CLK = OFMCLK / 7
                  8, APB1_CLK = OFMCLK / 8
                  9, APB1_CLK = OFMCLK / 9
                  10, APB1_CLK = OFMCLK / 10



             This property is **required**.

             Legal values: ``1``, ``2``, ``3``, ``4``, ``5``, ``6``, ``7``, ``8``, ``9``, ``10``

         * - ``apb2-prescaler``
           - ``int``
           - .. code-block:: none

                APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
                OFMCLK(MCLK) and needs to meet the following requirements.
                - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
                - APB2_CLK must be an integer division (including 1) of CORE_CLK.
                = Only the following values are allowed:
                  1, APB2_CLK = OFMCLK
                  2, APB2_CLK = OFMCLK / 2
                  3, APB2_CLK = OFMCLK / 3
                  4, APB2_CLK = OFMCLK / 4
                  5, APB2_CLK = OFMCLK / 5
                  6, APB2_CLK = OFMCLK / 6
                  7, APB2_CLK = OFMCLK / 7
                  8, APB2_CLK = OFMCLK / 8
                  9, APB2_CLK = OFMCLK / 9
                  10, APB2_CLK = OFMCLK / 10



             This property is **required**.

             Legal values: ``1``, ``2``, ``3``, ``4``, ``5``, ``6``, ``7``, ``8``, ``9``, ``10``

         * - ``apb3-prescaler``
           - ``int``
           - .. code-block:: none

                APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
                OFMCLK(MCLK) and needs to meet the following requirements.
                - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
                - APB3_CLK must be an integer division (including 1) of CORE_CLK.
                = Only the following values are allowed:
                  1, APB3_CLK = OFMCLK
                  2, APB3_CLK = OFMCLK / 2
                  3, APB3_CLK = OFMCLK / 3
                  4, APB3_CLK = OFMCLK / 4
                  5, APB3_CLK = OFMCLK / 5
                  6, APB3_CLK = OFMCLK / 6
                  7, APB3_CLK = OFMCLK / 7
                  8, APB3_CLK = OFMCLK / 8
                  9, APB3_CLK = OFMCLK / 9
                  10, APB3_CLK = OFMCLK / 10



             This property is **required**.

             Legal values: ``1``, ``2``, ``3``, ``4``, ``5``, ``6``, ``7``, ``8``, ``9``, ``10``

         * - ``apb4-prescaler``
           - ``int``
           - .. code-block:: none

                APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
                OFMCLK(MCLK) and needs to meet the following requirements.
                - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
                - APB4_CLK must be an integer division (including 1) of CORE_CLK.
                = Only the following values are allowed:
                  1, APB4_CLK = OFMCLK
                  2, APB4_CLK = OFMCLK / 2
                  3, APB4_CLK = OFMCLK / 3
                  4, APB4_CLK = OFMCLK / 4
                  5, APB4_CLK = OFMCLK / 5
                  6, APB4_CLK = OFMCLK / 6
                  7, APB4_CLK = OFMCLK / 7
                  8, APB4_CLK = OFMCLK / 8
                  9, APB4_CLK = OFMCLK / 9
                  10, APB4_CLK = OFMCLK / 10



             Legal values: ``1``, ``2``, ``3``, ``4``, ``5``, ``6``, ``7``, ``8``, ``9``, ``10``

         * - ``ram-pd-depth``
           - ``int``
           - .. code-block:: none

                Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
                Each bit in RAM_PDn can power down the relevant RAM block by setting
                itself to 1 for better power consumption and this valid bit-depth
                varies in different NPCX series.



             Legal values: ``8``, ``12``, ``15``

         * - ``pwdwn-ctl-val``
           - ``array``
           - .. code-block:: none

                Power-down (turn off clock) the modules during system initialization for
                better power consumption.



             This property is **required**.



   .. group-tab:: Deprecated node specific properties

      Deprecated properties not inherited from the base binding file.

      (None)

   .. group-tab:: Base properties

      Properties inherited from the base binding file, which defines
      common properties that may be set on many nodes. Not all of these
      may apply to the "nuvoton,npcx-pcc" compatible.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``wakeup-source``
           - ``boolean``
           - .. code-block:: none

                Property to identify that a device can be used as wake up source.

                When this property is provided a specific flag is set into the
                device that tells the system that the device is capable of
                wake up the system.

                Wake up capable devices are disabled (interruptions will not wake up
                the system) by default but they can be enabled at runtime if necessary.



         * - ``power-domain``
           - ``phandle``
           - .. code-block:: none


                Power domain the device belongs to.

                The device will be notified when the power domain it belongs to is either
                suspended or resumed.



         * - ``zephyr,pm-device-runtime-auto``
           - ``boolean``
           - .. code-block:: none

                Automatically configure the device for runtime power management after the
                init function runs.



         * - ``zephyr,disabling-power-states``
           - ``phandles``
           - .. code-block:: none

                List of power states that will disable this device power.



         * - ``status``
           - ``string``
           - .. code-block:: none

                indicates the operational status of a device


             Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``

             See :ref:`dt-important-props` for more information.

         * - ``compatible``
           - ``string-array``
           - .. code-block:: none

                compatible strings


             This property is **required**.

             See :ref:`dt-important-props` for more information.

         * - ``reg``
           - ``array``
           - .. code-block:: none

                register space


             This property is **required**.

             See :ref:`dt-important-props` for more information.

         * - ``reg-names``
           - ``string-array``
           - .. code-block:: none

                name of each register space


         * - ``interrupts``
           - ``array``
           - .. code-block:: none

                interrupts for device


             See :ref:`dt-important-props` for more information.

         * - ``interrupts-extended``
           - ``compound``
           - .. code-block:: none

                extended interrupt specifier for device


         * - ``interrupt-names``
           - ``string-array``
           - .. code-block:: none

                name of each interrupt


         * - ``interrupt-parent``
           - ``phandle``
           - .. code-block:: none

                phandle to interrupt controller node


         * - ``label``
           - ``string``
           - .. code-block:: none

                Human readable string describing the device (used as device_get_binding() argument)



             See :ref:`dt-important-props` for more information.

             This property is **deprecated**.

         * - ``clocks``
           - ``phandle-array``
           - .. code-block:: none

                Clock gate information


         * - ``clock-names``
           - ``string-array``
           - .. code-block:: none

                name of each clock


         * - ``#address-cells``
           - ``int``
           - .. code-block:: none

                number of address cells in reg property


         * - ``#size-cells``
           - ``int``
           - .. code-block:: none

                number of size cells in reg property


         * - ``dmas``
           - ``phandle-array``
           - .. code-block:: none

                DMA channels specifiers


         * - ``dma-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of DMA channel specifiers


         * - ``io-channels``
           - ``phandle-array``
           - .. code-block:: none

                IO channels specifiers


         * - ``io-channel-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of IO channel specifiers


         * - ``mboxes``
           - ``phandle-array``
           - .. code-block:: none

                mailbox / IPM channels specifiers


         * - ``mbox-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of mailbox / IPM channel specifiers


         * - ``zephyr,deferred-init``
           - ``boolean``
           - .. code-block:: none

                Do not initialize device automatically on boot. Device should be manually
                initialized using device_init().






Specifier cell names
********************

- clock cells: bus, ctl, bit

Part 3

한국어 전문 번역

nuvoton,npcx-pcc

Vendor: Nuvoton Technology Corporation

공식 설명

Nuvoton, NPCX PCC (Power and Clock Controller) node.
Besides power management, this node is also in charge of configuring the
Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
and most of NPCX hardware modules.

Here is an example of configuring OFMCLK and the other clock sources derived
from it in board dts file.
&pcc {
  clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
  core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
  apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
  apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
  apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
};

NPCX Power and Clock Controller가 HFCG에서 만든 OFMCLK와 core·APB clock을 구성하는 binding입니다.

OFMCLK와 bus clock

OFMCLK는 HFCG에서 나온 Cortex-M4 core와 다수 hardware module의 source clock입니다. clock-frequency는 48·50·66·80·90·96·100·120 MHz만 허용합니다. core-prescaler는 OFMCLK를 1~10으로 나눠 CORE_CLK를 4~100 MHz 범위에 맞춥니다.

APB1은 4~50 MHz, APB2·APB4는 8~50 MHz, APB3는 12.5~50 MHz여야 합니다. 각 APB clock은 CORE_CLK의 정수 분주여야 하며 APB1~3 prescaler는 필수, APB4는 optional입니다.

DTS 설정 예제

&pcc {
  clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
  core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
  apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
  apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
  apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
};

이 예제는 OFMCLK 100 MHz를 divider 5로 나눠 core와 APB1~3을 20 MHz로 만듭니다.

Power-down과 specifier

ram-pd-depth는 RAM_PD register의 유효 bit depth 8·12·15 중 하나입니다. pwdwn-ctl-val은 초기화 때 clock을 끌 module 배열이며 필수입니다. Clock specifier cell은 bus, ctl, bit입니다. compatible와 reg도 필수입니다.

Property

공식 Zephyr 3.7.0 schema의 모든 property를 옮겼습니다. Type과 required·deprecated·constant·default·legal value를 원문에서 직접 추출했습니다.

노드 전용 속성 · 9개
이름형식설명과 제약
#clock-cellsintConsumer의 clock specifier에서 기대할 item 수입니다.
필수
clock-frequencyintHFCG output인 OFMCLK의 기본 frequency를 Hz 단위로 지정합니다.
필수 · 허용값: 120000000, 100000000, 96000000, 90000000, 80000000, 66000000, 50000000, 48000000
core-prescalerintOFMCLK를 나눠 CORE_CLK를 만드는 FPRED prescaler입니다.
필수 · 허용값: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
apb1-prescalerintOFMCLK를 나눠 APB1_CLK를 만드는 prescaler입니다.
필수 · 허용값: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
apb2-prescalerintOFMCLK를 나눠 APB2_CLK를 만드는 prescaler입니다.
필수 · 허용값: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
apb3-prescalerintOFMCLK를 나눠 APB3_CLK를 만드는 prescaler입니다.
필수 · 허용값: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
apb4-prescalerintOFMCLK를 나눠 APB4_CLK를 만드는 optional prescaler입니다.
허용값: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
ram-pd-depthintRAM block Power-Down control(RAM_PD) register에서 유효한 bit depth입니다.
허용값: 8, 12, 15
pwdwn-ctl-valarraySystem initialization 중 clock을 끌 module을 지정하는 power-down control 값 배열입니다.
필수
Base binding property · 24개

공식 문서의 기본 속성을 빠짐없이 실었습니다.

이름형식설명과 제약
wakeup-sourceboolean이 장치를 시스템 깨우기에 사용할 수 있음을 나타냅니다. 이 속성이 있으면 깨우기 지원 플래그가 설정됩니다. 기본 상태에서는 장치의 인터럽트로 시스템을 깨우지 않으며, 실행 중에 깨우기 기능을 활성화할 수 있습니다.
power-domainphandle장치가 속한 전원 도메인의 phandle입니다. 해당 전원 도메인이 일시 중단되거나 다시 동작하면 장치에 알림이 전달됩니다.
zephyr,pm-device-runtime-autoboolean초기화 함수 실행 후 장치의 런타임 전원 관리를 자동으로 설정합니다.
zephyr,disabling-power-statesphandles이 장치의 전원이 꺼지는 전원 상태 목록입니다.
statusstring장치의 동작 상태를 나타냅니다.
허용값: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss'
compatiblestring-array이 노드에 적용할 바인딩과 드라이버를 식별하는 compatible 문자열 목록입니다.
필수
regarray장치 레지스터의 주소 범위를 지정합니다.
필수
reg-namesstring-array각 register space의 이름입니다.
interruptsarray장치에서 사용하는 인터럽트를 지정하는 목록입니다.
interrupts-extendedcompound인터럽트 컨트롤러의 phandle을 함께 지정하는 확장 형식의 인터럽트 명세입니다.
interrupt-namesstring-array각 interrupt의 이름입니다.
interrupt-parentphandle인터럽트 컨트롤러 노드를 가리키는 phandle입니다.
labelstring사람이 장치를 알아볼 수 있도록 붙이는 이름입니다. 과거에는 device_get_binding()의 인자로 사용했습니다.
사용 중단됨
clocksphandle-array클록 게이트 또는 클록 공급원을 지정하는 phandle 배열입니다.
clock-namesstring-array각 clock의 이름입니다.
#address-cellsint하위 노드의 reg 속성에서 주소를 나타내는 데 쓰는 셀 수입니다.
#size-cellsint하위 노드의 reg 속성에서 크기를 나타내는 데 쓰는 셀 수입니다.
dmasphandle-arrayDMA 채널을 지정하는 phandle 배열입니다.
dma-namesstring-array지정한 DMA 채널의 이름입니다.
io-channelsphandle-arrayI/O 채널을 지정하는 phandle 배열입니다.
io-channel-namesstring-array지정한 I/O 채널의 이름입니다.
mboxesphandle-array메일박스/IPM 채널을 지정하는 phandle 배열입니다.
mbox-namesstring-array지정한 메일박스/IPM 채널의 이름입니다.
zephyr,deferred-initboolean부팅할 때 장치를 자동으로 초기화하지 않습니다. 이후 device_init()를 호출해 직접 초기화해야 합니다.

지정자 셀 이름

Clock specifier의 세 cell은 bus, ctl, bit입니다.

Source

출처

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