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Zephyr 3.7.0 · Boards · WeAct · USB-C PD

WeAct STM32G431 Core

CC1/CC2·dead-battery 배선, UCPD pin 예약과 DFU workaround를 설명합니다.

Official pathboards/weact/stm32g431_core/doc/index.html
Source fileboards/weact/stm32g431_core/doc/index.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

지원표 6행과 solder bridge 6행, USB-C PD 안전 경고·clock·DFU를 보존했습니다.

MCU

STM32G431CB

System

144MHz PLL

USB-C

UCPD optional

Reserved

PA9/10 · PB2/4/6

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 757F23A0FE4BE560447ABDB77BCB775276D4EF669F3CF6A9097F2EF82A3EC9B7
.. _weact_stm32g431_core:

WeAct Studio STM32G431 Core Board
#################################

The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development
board. See the `STM32G431CB website`_ for more information about the MCU. More information
about the board, including schematics, is available from the `WeAct GitHub`_.

Modifications USB-C Power Delivery
**********************************

The board does not support USB-C PD in its standard configuration. To enable USB-C PD, CC1
and CC2 need to be disconnected from their pull-down resistors and be connected to PB6 and
PB4 respectively. Dead battery support requires PA9 and PA10 to be routed to CC1 and
CC2. VBUS also needs to be connected to the MCU through a voltage divider.

The pull-downs are disconnected by removing the zero-Ohm resistors on SB8 and SB9 next to
the USB-C connector. SB3, SB5, SB6, and SB7 then need to be closed to connect the CCx
lines to the MCU. The voltage divider is connected to PB2 by closing SB4.

After these modifications have been made, PA9, PA10, PB2, PB4, and PB6 should be
considered reserved for USB-C and not available for other applications.

.. warning::
   The internal USB DFU boot loader may not work correctly with machines that respect USB
   PD signaling unless dead battery support has been enabled. A USB-C to USB-A adapter or
   programming using the SWD port can be used as a workaround.


Supported Features
==================

The Zephyr weact_stm32g431_core board configuration supports the following hardware
features:

+------------+------------+-------------------------------------+
| Interface  | Controller | Driver/Component                    |
+============+============+=====================================+
| NVIC       | on-chip    | nested vector interrupt controller  |
+------------+------------+-------------------------------------+
| UART       | on-chip    | serial port                         |
+------------+------------+-------------------------------------+
| GPIO       | on-chip    | gpio                                |
+------------+------------+-------------------------------------+
| ADC        | on-chip    | ADC Controller                      |
+------------+------------+-------------------------------------+
| USB        | on-chip    | USB device                          |
+------------+------------+-------------------------------------+
| UCPD       | on-chip    | ucpd                                |
+------------+------------+-------------------------------------+

The default configuration can be found in the defconfig file:

:zephyr_file:`boards/weact/stm32g431_core/weact_stm32g431_core_defconfig`

Pin Mapping
===========

Default Zephyr Peripheral Mapping:
----------------------------------

- UART_2 TX/RX   : PA2/PA3
- UCPD1 CCx      : PB6/PB4 (not connected by default)
- UCPD1 DBCCx    : PA9/PA10 (not connected by default)
- BUTTON (User)  : PC13
- BUTTON (BOOT0) : PB8
- LED0           : PC6
- ADC (VBUS)     : PB2

The ADC is disabled by default since the VBUS voltage divider is not connected in the
board's standard configuration.


Hardware Configuration
----------------------
+---------------+---------+-----------------------------------------------+
| Solder bridge | Default | Description                                   |
+===============+=========+===============================================+
| SB1/SB2       | Open    | Route PC14/PC15 (LSE) to header               |
+---------------+---------+-----------------------------------------------+
| SB6/SB7       | Open    | Connect PB4/PB6 (UCPD1_CCx) to USB-C CCx pins |
+---------------+---------+-----------------------------------------------+
| SB3/SB5       | Open    | Connect PA9/PA10 (UCPD1_DBCCx) to PB6/PB4     |
+---------------+---------+-----------------------------------------------+
| SB4           | Open    | Connect PB2 to VBUS voltage divider           |
+---------------+---------+-----------------------------------------------+
| SB8/SB9       | Closed  | Connect USB-CCx to pull-down resistors        |
+---------------+---------+-----------------------------------------------+
| SB10          | Open    | VBUS protection diode bypass                  |
+---------------+---------+-----------------------------------------------+


Clock Sources
-------------

The board has two external oscillators. The frequency of the slow clock (LSE) is 32.768
kHz. The frequency of the main clock (HSE) is 8 MHz.

The default configuration sources the system clock from the PLL, which is derived from
HSE, and is set at 144 MHz. The 48 MHz clock used by the USB interface is derived from the
PLL instead of the internal 48 MHz oscillator.

Programming and Debugging
*************************

The MCU is normally programmed using the ROM bootloader or the exposed SWD port.

Please note that some laptops may not detect the ROM bootloader correctly if the CCx
pull-downs have been disconnected by opening SB8 and SB9 unless dead battery support has
been enabled by closing SB3 and SB5. A USB-C to USB-A adapter can be used as a workaround
if this is a problem.

Flashing an Application
=======================

Connect a USB-C cable and the board should power ON. Force the board into DFU mode by
keeping the BOOT0 switch pressed while pressing and releasing the NRST switch.

The dfu-util runner is supported on this board and so a sample can be built and tested
easily.

.. zephyr-app-commands::
   :zephyr-app: samples/basic/blinky
   :board: weact_stm32g431_core
   :goals: build flash

Debugging
=========

The board can be debugged by installing the included 100 mil (0.1 inch) header, and
attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO pins on that header.


References
**********

.. target-notes::

.. _WeAct GitHub:
   https://github.com/WeActStudio/WeActStudio.STM32G431CoreBoard

.. _STM32G431CB website:
   https://www.st.com/en/microcontrollers-microprocessors/stm32g431cb.html

.. _STM32F401x reference manual:
   https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Part 3

한국어 전문 번역

개요

WeAct STM32G431 Core는 STM32G431 기반 저가형 최소 구성 development board입니다.

USB-C Power Delivery 개조

Standard configuration은 USB-C PD를 지원하지 않습니다. PD를 활성화하려면 CC1·CC2를 pull-down resistor에서 분리해 각각 PB6·PB4에 연결합니다. Dead-battery support에는 PA9·PA10을 각각 CC1·CC2로 route해야 하고 VBUS도 voltage divider를 거쳐 MCU에 연결해야 합니다.

USB-C connector 옆 SB8·SB9의 0Ω resistor를 제거해 pull-down을 분리합니다. 이어 SB3·SB5·SB6·SB7을 닫아 CCx line을 MCU에 연결하고 SB4를 닫아 voltage divider를 PB2에 연결합니다. 개조 후 PA9, PA10, PB2, PB4, PB6은 USB-C 전용으로 예약해야 합니다.

지원 기능

InterfaceControllerDriver/Component
NVICon-chipnested vector interrupt controller
UARTon-chipserial port
GPIOon-chipgpio
ADCon-chipADC Controller
USBon-chipUSB device
UCPDon-chipucpd

Default configuration은 boards/weact/stm32g431_core/weact_stm32g431_core_defconfig에 있습니다.

Pin mapping

  • UART_2 TX/RX: PA2/PA3
  • UCPD1 CCx: PB6/PB4, default 미연결
  • UCPD1 DBCCx: PA9/PA10, default 미연결
  • User button: PC13
  • BOOT0 button: PB8
  • LED0: PC6
  • ADC(VBUS): PB2

Standard board에는 VBUS voltage divider가 연결되지 않아 ADC가 default로 비활성화됩니다.

Hardware configuration

Solder bridgeDefaultDescription
SB1/SB2OpenPC14/PC15(LSE)를 header로 route
SB6/SB7OpenPB4/PB6(UCPD1_CCx)를 USB-C CCx에 연결
SB3/SB5OpenPA9/PA10(UCPD1_DBCCx)를 PB6/PB4에 연결
SB4OpenPB2를 VBUS voltage divider에 연결
SB8/SB9ClosedUSB-CCx를 pull-down resistor에 연결
SB10OpenVBUS protection diode bypass

Clock source

LSE external oscillator는 32.768kHz, HSE는 8MHz입니다. Default system clock은 HSE에서 유도한 PLL의 144MHz입니다. USB용 48MHz clock도 internal 48MHz oscillator가 아니라 PLL에서 유도합니다.

Programming과 debugging

ROM bootloader 또는 노출된 SWD port로 program합니다. SB8·SB9를 열어 CCx pull-down을 분리했지만 SB3·SB5를 닫아 dead-battery support를 활성화하지 않았다면 일부 laptop이 ROM bootloader를 감지하지 못할 수 있습니다. USB-C-to-USB-A adapter가 workaround입니다.

Application flash

USB-C cable을 연결한 뒤 BOOT0을 누른 상태에서 NRST를 눌렀다 놓아 DFU mode로 진입합니다.

west build -b weact_stm32g431_core samples/basic/blinky
west flash

Debug

100mil(0.1-inch) header를 설치하고 SWD debugger를 3V3, GND, SCK, DIO pin에 연결합니다.

참고 자료

Source

출처

영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.