Part 1
요약·해설
MAX 10 Nios II timer·UART·SLIP, 미지원 peripheral과 실행 전문 번역.
Altera Nios II
50 MHz
SLIP only
Part 2
접을 수 있는 영어 원문 전체
영어 원문 전체 펼치기
B44C2ED33EF33C5AD9B72F40C4D61D663077CE11F0A7ABE9043FC16781874B7A
.. _qemu_nios2:
Altera Nios-II Emulation (QEMU)
###############################
Overview
********
This board configuration will use QEMU to emulate the Altera MAX 10 platform.
This configuration provides support for an Altera Nios-II CPU and these devices:
* Internal Interrupt Controller
* Altera Avalon Timer
* NS16550 UART
.. note::
This board configuration makes no claims about its suitability for use
with an actual ti_lm3s6965 hardware system, or any other hardware system.
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| IIC | on-chip | Internal interrupt |
| | | controller |
+--------------+------------+----------------------+
| NS16550 | on-chip | serial port |
| UART | | |
+--------------+------------+----------------------+
| TIMER | on-chip | system clock |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 50 MHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART0.
If SLIP networking is enabled (see below), an additional serial port will be
used for it.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Memory protection through optional MPU. However, using a XIP kernel
effectively provides TEXT/RODATA write protection in ROM.
* Writing to the hardware's flash memory
* Serial port in Direct Memory Access (DMA) mode
* Serial Peripheral Interface (SPI) flash
* General-Purpose Input/Output (GPIO)
* Inter-Integrated Circuit (I2C)
* Ethernet
Programming and Debugging
*************************
Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_nios2
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
Networking
==========
The board supports SLIP networking over an emulated serial port
(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
:ref:`networking_with_qemu`.
References
**********
* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_
* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_
* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_
* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_
* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_
* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_
* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite
Part 3
한국어 전문 번역
개요
이 board 구성은 QEMU로 Altera MAX 10 platform을 emulation합니다. Altera Nios II CPU, internal interrupt controller, Altera Avalon timer, NS16550 UART를 지원합니다.
지원 기능
| 인터페이스 | 컨트롤러 | 드라이버/컴포넌트 |
|---|---|---|
IIC | on-chip | internal interrupt controller |
NS16550 UART | on-chip | serial port |
TIMER | on-chip | system clock |
Kernel은 현재 이 platform의 다른 하드웨어 기능을 지원하지 않습니다.
장치
System clock
System clock frequency는 50 MHz입니다.
Serial port
CPU UART0 하나를 사용합니다. SLIP networking을 켜면 serial port 하나를 추가로 사용합니다.
알려진 문제와 제한
- Optional MPU memory protection 미지원. XIP kernel은 ROM의 TEXT/RODATA 쓰기 보호 효과를 제공합니다.
- Hardware flash 쓰기 미지원
- Serial DMA mode 미지원
- SPI flash, GPIO, I2C, Ethernet 미지원
프로그래밍과 디버깅
synchronization sample을 다음처럼 실행합니다.
# Unix host의 Zephyr 저장소 루트에서
west build -b qemu_nios2 samples/synchronization -t run
***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
Ctrl+A 뒤 x로 종료합니다. Debug는 일반 Zephyr debugging 절차를 따릅니다.
Networking
CONFIG_NET_SLIP_TAP=y로 emulated serial port를 통한 SLIP networking을 지원합니다.
참고 자료
Source
출처
영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.