boards/qemu/malta/doc/index.html · boards/qemu/malta/doc/index.rst 공식 원문 ↗

Zephyr 3.7.0 · Boards · QEMU

QEMU MIPS Malta

MIPS Malta를 little-endian 또는 big-endian으로 emulation하는 구성입니다.

Official pathboards/qemu/malta/doc/index.html
Source fileboards/qemu/malta/doc/index.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

MIPS 4Kc/24Kc와 big-endian target, CP0 timer·UART 실행 전문 번역.

CPU

MIPS 4Kc/24Kc

Clock

CP0 · 200 MHz

Endian

LE · BE target

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 82822AEE9E49F27EC7CFB611E13A411AB034EB039C081F90667AA4ADC853C01A
.. _qemu_malta:

MIPS Malta Emulation (QEMU)
###########################

Overview
********

This board configuration will use QEMU to emulate the MIPS Malta platform.

This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices:

* CP0 Interrupt Controller
* CP0 Core Timer
* NS16550 UART


.. note::
   This board configuration makes no claims about its suitability for use
   with an actual MIPS Malta hardware system, or any other hardware system.

Hardware
********

Supported Features
==================

The following hardware features are supported:

+----------------+------------+----------------------+
| Interface      | Controller | Driver/Component     |
+================+============+======================+
| CP0 IntC       | on-chip    | interrupt controller |
+----------------+------------+----------------------+
| CP0 Core Timer | on-chip    | system clock         |
+----------------+------------+----------------------+
| NS16550        | FPGA       | serial port          |
| UART           |            |                      |
+----------------+------------+----------------------+

The kernel currently does not support other hardware features on this platform.

Devices
========
System Clock
------------

Qemu CP0 timer uses a clock frequency of 200 MHz,
see target/mips/cp0_timer.c in Qemu source tree for details.

Serial Port
-----------

This board configuration uses a single serial communication channel
with the FPGA UART2.

Programming and Debugging
*************************

Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:

.. zephyr-app-commands::
   :zephyr-app: samples/synchronization
   :host-os: unix
   :board: qemu_malta
   :goals: run

This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:

.. code-block:: console

        *** Booting Zephyr OS build v2.7.99-1627-g9bea7790d620  ***
        thread_a: Hello World from cpu 0 on qemu_malta!
        thread_b: Hello World from cpu 0 on qemu_malta!
        thread_a: Hello World from cpu 0 on qemu_malta!
        thread_b: Hello World from cpu 0 on qemu_malta!
        thread_a: Hello World from cpu 0 on qemu_malta!
        thread_b: Hello World from cpu 0 on qemu_malta!
        thread_a: Hello World from cpu 0 on qemu_malta!
        thread_b: Hello World from cpu 0 on qemu_malta!
        thread_a: Hello World from cpu 0 on qemu_malta!
        thread_b: Hello World from cpu 0 on qemu_malta!


Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.


Big-Endian
==========

Use this configuration to run :zephyr:code-sample:`synchronization` sample in big-endian mode:

.. zephyr-app-commands::
   :zephyr-app: samples/synchronization
   :host-os: unix
   :board: qemu_malta/qemu_malta/be
   :goals: run


References
**********

https://www.qemu.org/
https://www.linux-mips.org/wiki/MIPS_Malta

Part 3

한국어 전문 번역

개요

이 board 구성은 QEMU로 MIPS Malta platform을 emulation합니다. MIPS 4Kc/24Kc CPU core, CP0 interrupt controller, CP0 core timer, NS16550 UART를 지원합니다.

지원 기능

인터페이스컨트롤러드라이버/컴포넌트
CP0 IntCon-chipinterrupt controller
CP0 Core Timeron-chipsystem clock
NS16550 UARTFPGAserial port

Kernel은 현재 이 platform의 다른 하드웨어 기능을 지원하지 않습니다.

장치

System clock

QEMU CP0 timer는 200 MHz clock을 사용합니다. 자세한 구현은 QEMU source tree의 target/mips/cp0_timer.c에 있습니다.

Serial port

FPGA UART2 하나를 serial communication channel로 사용합니다.

프로그래밍과 디버깅

QEMU에서 기본 Zephyr application과 kernel test를 실행합니다. 다음은 little-endian synchronization sample 예입니다.

# Unix host의 Zephyr 저장소 루트에서
west build -b qemu_malta samples/synchronization -t run
*** Booting Zephyr OS build v2.7.99-1627-g9bea7790d620  ***
thread_a: Hello World from cpu 0 on qemu_malta!
thread_b: Hello World from cpu 0 on qemu_malta!
thread_a: Hello World from cpu 0 on qemu_malta!
thread_b: Hello World from cpu 0 on qemu_malta!
thread_a: Hello World from cpu 0 on qemu_malta!
thread_b: Hello World from cpu 0 on qemu_malta!
thread_a: Hello World from cpu 0 on qemu_malta!
thread_b: Hello World from cpu 0 on qemu_malta!
thread_a: Hello World from cpu 0 on qemu_malta!
thread_b: Hello World from cpu 0 on qemu_malta!

Ctrl+A를 누른 뒤 x를 눌러 QEMU를 종료합니다.

Big-endian

Big-endian mode에서는 별도 target을 사용합니다.

# Unix host의 Zephyr 저장소 루트에서
west build -b qemu_malta/qemu_malta/be samples/synchronization -t run

참고 자료

Source

출처

영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.