QEMU Arm Cortex-R5 한국어 번역

Part 1

요약·해설

1000 Hz TTC tick, UART0, DCLS 미emulation과 tickless 제한을 설명합니다.

CPU

Cortex-R5 · ZynqMP

Timer

TTC · 1000 Hz

Limits

No DCLS · no tickless

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기

원문 SHA-256 2076E686AA59DDC397B86E6E147CD95863A7888F406266D3B2A76078141F7775

.. _qemu_cortex_r5:

ARM Cortex-R5 Emulation (QEMU)
##############################

Overview
********

This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+
(ZynqMP) platform.

This configuration provides support for an ARM Cortex-R5 CPU and these devices:

* ARM PL-390 Generic Interrupt Controller
* Xilinx Zynq TTC (Cadence TTC)
* Xilinx Zynq UART

.. note::
   This board configuration makes no claims about its suitability for use
   with an actual ZCU102 hardware system, or any other hardware system.

Hardware
********
Supported Features
==================

The following hardware features are supported:

+--------------+------------+----------------------+
| Interface    | Controller | Driver/Component     |
+==============+============+======================+
| GIC          | on-chip    | generic interrupt    |
|              |            | controller           |
+--------------+------------+----------------------+
| TTC          | on-chip    | system timer         |
+--------------+------------+----------------------+
| UART         | on-chip    | serial port          |
+--------------+------------+----------------------+

The kernel currently does not support other hardware features on this platform.

Devices
========
System Timer
------------

This board configuration uses a system timer tick frequency of 1000 Hz.

Serial Port
-----------

This board configuration uses a single serial communication channel with the
on-chip UART0.

Known Problems or Limitations
==============================

The following platform features are unsupported:

* Dual-redundant Core Lock-step (DCLS) execution is not emulated.
* Xilinx Zynq TTC driver does not support tickless mode operation.

Programming and Debugging
*************************

Use this configuration to run basic Zephyr applications and kernel tests in the
QEMU emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:

.. zephyr-app-commands::
   :zephyr-app: samples/synchronization
   :host-os: unix
   :board: qemu_cortex_r5
   :goals: run

This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:

.. code-block:: console

        *** Booting Zephyr OS build v2.2.0  ***
        threadA: Hello World from qemu_cortex_r5!
        threadB: Hello World from qemu_cortex_r5!
        threadA: Hello World from qemu_cortex_r5!
        threadB: Hello World from qemu_cortex_r5!
        threadA: Hello World from qemu_cortex_r5!
        threadB: Hello World from qemu_cortex_r5!
        threadA: Hello World from qemu_cortex_r5!
        threadB: Hello World from qemu_cortex_r5!
        threadA: Hello World from qemu_cortex_r5!
        threadB: Hello World from qemu_cortex_r5!

Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.

Debugging
=========

Refer to the detailed overview about :ref:`application_debugging`.

References
**********

1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414)
2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)
3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Part 3

한국어 전문 번역

개요

이 board 구성은 QEMU로 Xilinx Zynq UltraScale+(ZynqMP) platform을 emulation합니다. Arm Cortex-R5 CPU, ARM PL-390 GIC, Xilinx Zynq TTC(Cadence TTC), Xilinx Zynq UART를 지원합니다.

지원 기능

인터페이스	컨트롤러	드라이버/컴포넌트
`GIC`	`on-chip`	`generic interrupt controller`
`TTC`	`on-chip`	`system timer`
`UART`	`on-chip`	`serial port`

Kernel은 현재 이 platform의 다른 하드웨어 기능을 지원하지 않습니다.

장치

System timer

System timer tick frequency는 1000 Hz입니다.

Serial port

On-chip UART0 하나를 사용합니다.

알려진 문제와 제한

Dual-redundant Core Lock-step(DCLS) 실행은 emulation하지 않습니다.
Xilinx Zynq TTC driver는 tickless mode를 지원하지 않습니다.

프로그래밍과 디버깅

이 구성은 QEMU emulated environment에서 기본 Zephyr application과 kernel test를 실행할 때 사용합니다. 다음은 synchronization sample 예입니다.

# Unix host의 Zephyr 저장소 루트에서
west build -b qemu_cortex_r5 samples/synchronization -t run

Image를 build하고 QEMU로 boot하면 다음 console output이 표시됩니다.

*** Booting Zephyr OS build v2.2.0  ***
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!

Ctrl+A를 누른 뒤 x를 눌러 QEMU를 종료합니다.

Debug

일반 Zephyr application debugging 절차를 따릅니다.

참고 자료

ARMv7-A and ARMv7-R Architecture Reference Manual, ARM DDI 0406C ID051414
Cortex-R5 and Cortex-R5F Technical Reference Manual, ARM DDI 0460C ID021511
Zynq UltraScale+ Device Technical Reference Manual, UG1085

Source

출처

영어 원문에는 문단, 문서 지시문, 표, 코드, 코드 심벌, 경로를 그대로 보존했습니다.