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Zephyr 3.7.0 · Boards · Microchip · PolarFire SoC · RISC-V

Microchip PolarFire SoC Icicle

MPFS250T PolarFire SoC FPGA와 RISC-V E51을 위한 Icicle development board입니다.

Official pathboards/microchip/mpfs_icicle/doc/index.html
Source fileboards/microchip/mpfs_icicle/doc/index.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

Single target와 SMP variant build, RV64 OpenOCD/GDB load 절차를 다룹니다.

SoC FPGA

Microchip MPFS250T

CPU

E51 RISC-V · RV64

Variants

mpfs_icicle · polarfire/smp

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 C4BD7D70B7284280E64C0FF641D380AF9EC723E28329634D7CAC0C31EAFFDC01
.. _mpfs_icicle:

Microchip mpfs_icicle
#####################

Overview
********

The Microchip mpfs_icicle board is a PolarFire SoC FPGA based development board with a Microchip MPFS250T fpga device.
The E51 RISC-V CPU can be deployed on the mpfs_icicle board.
More information can be found on the `Microchip website <https://www.microchip.com/en-us/product/MPFS250T>`_.

Programming and debugging
*************************

Building
========

Applications for the ``mpfs_icicle`` board configuration can be built as usual
(see :ref:`build_an_application`):

.. zephyr-app-commands::
   :board: mpfs_icicle
   :goals: build

To build the default SMP capable variant

.. zephyr-app-commands::
   :board: mpfs_icicle/polarfire/smp
   :goals: build

Flashing
========

In order to upload the application to the device, you'll need OpenOCD and GDB
with RISC-V support.
You can get them as a part of SoftConsole SDK.
Download and installation instructions can be found on
`Microchip's SoftConsole website
<https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/programming-and-debug/softconsole>`_.

With the necessary tools installed, you can connect to the board using OpenOCD.
To establish an OpenOCD connection run:

.. code-block:: bash

   sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
   <softconsole_path>/openocd/bin/openocd  --file \
   <softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg


Leave it running, and in a different terminal, use GDB to upload the binary to
the board. You can use the RISC-V GDB from a toolchain delivered with
SoftConsole SDK.

Here is the GDB terminal command to connect to the device
and load the binary:

.. code-block:: console

   <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
   -ex "target extended-remote localhost:3333" \
   -ex "set mem inaccessible-by-default off" \
   -ex "set arch riscv:rv64" \
   -ex "set riscv use_compressed_breakpoints no" \
   -ex "load" <path_to_executable>

Debugging
=========

Refer to the detailed overview of :ref:`application_debugging`.

Part 3

한국어 전문 번역

개요

Microchip mpfs_icicle board는 Microchip MPFS250T FPGA device를 탑재한 PolarFire SoC FPGA 기반 development board입니다. E51 RISC-V CPU를 이 board에서 실행할 수 있습니다. 자세한 내용은 Microchip MPFS250T website에서 확인할 수 있습니다.

Programming과 Debugging

Building

mpfs_icicle board configuration의 application은 일반적인 방식으로 build할 수 있습니다.

west build -b mpfs_icicle

Default SMP-capable variant를 build하려면 다음 명령을 사용합니다.

west build -b mpfs_icicle/polarfire/smp

Flashing

Application을 device에 upload하려면 RISC-V를 지원하는 OpenOCD와 GDB가 필요합니다. 두 도구는 SoftConsole SDK에 포함되며 download와 installation 방법은 Microchip SoftConsole website에서 확인할 수 있습니다.

필요한 도구를 설치한 뒤 다음 명령으로 OpenOCD connection을 시작합니다.

sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
<softconsole_path>/openocd/bin/openocd  --file \
<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg

OpenOCD를 실행한 채 다른 terminal에서 SoftConsole SDK toolchain의 RISC-V GDB를 사용해 binary를 board에 upload합니다. 다음 명령은 device에 연결하고 executable을 load합니다.

<softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
-ex "target extended-remote localhost:3333" \
-ex "set mem inaccessible-by-default off" \
-ex "set arch riscv:rv64" \
-ex "set riscv use_compressed_breakpoints no" \
-ex "load" <path_to_executable>

Debugging

세부 절차는 Zephyr의 Application Debugging 안내를 참고하십시오.

Source

출처

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