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Zephyr 3.7.0 · Boards · Intel SoC FPGA

Intel Agilex SoC Development Kit

Quad Cortex-A53와 DDR4를 통합한 Agilex F-Series SoC FPGA development kit입니다.

Official pathboards/intel/socfpga/agilex_socdk/doc/index.html
Source fileboards/intel/socfpga/agilex_socdk/doc/index.rst
Source versionZephyr 3.7.0
TranslationFull · reviewed

본문 기준: Zephyr 3.7.0 LTS3 · 이후 유지보수 패치는 별도입니다.

Part 1

요약·해설

Agilex F-Series FPGA, quad Cortex-A53, 8GB DDR4와 ATF boot flow를 설명합니다.

CPU

4x Cortex-A53

Memory

8GB DDR4

Load

0x10000000

Part 2

접을 수 있는 영어 원문 전체

영어 원문 전체 펼치기
원문 SHA-256 5C2F63C4D637966712A6F19FFE9A1E7BCAC73C81ADFECB49A0139D1F20E90FB4
.. _intel_socfpga_agilex_socdk:

Intel Agilex SoC Development Kit
#################################

Overview
********

The Intel Agilex SoC Development Kit offers a complete design environment
that includes both hardware and software for developing Intel Agilex
F-Series FPGA designs. This kit is recommended for developing custom
Arm* processor-based SoC designs and evaluating transceiver performance.

Hardware
********

The Intel Agilex SoC Development Kit supports the following physical features:

- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the
  quad-core Arm Cortex-A53 processor
- On-board 8 GB DDR4 memory
- On-board JTAG Intel FPGA Download Cable II
- QSPI flash daughtercard
- HPS OOBE daughtercard with UART and SD Card support

Supported Features
==================
The Intel Agilex SoC Development Kit configuration supports the following
hardware features:

+-----------+------------+--------------------------------------+
| Interface | Controller | Driver/Component                     |
+===========+============+======================================+
| GIC-400   | on-chip    | GICv2 interrupt controller           |
+-----------+------------+--------------------------------------+
| ARM TIMER | on-chip    | System Clock                         |
+-----------+------------+--------------------------------------+
| UART      | on-chip    | NS16550 compatible serial port       |
+-----------+------------+--------------------------------------+

Other hardware features have not been enabled yet for this board.

The default configuration can be found in
:zephyr_file:`boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig`

Programming and Debugging
*************************

Boot Flow
=========
Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF).
ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage
boot loader (SSBL).

Zephyr boot flow:

        ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1)

Intel Arm Trusted Firmware (ATF) can be downloaded from github:

        `altera-opensource/arm-trusted-firmware <https://github.com/altera-opensource/arm-trusted-firmware.git>`_

Flashing
========
Zephyr image can be loaded in DDR memory at address 0x10000000 from
SD Card or QSPI Flash in ATF BL2.

Debugging
=========
The Intel Agilex SoC Development Kit includes one JTAG connector on
board, connect it to Intel USB blaster download cables for debugging.

Zephyr applications running on the Cortex-A53 core can be tested by
observing UART console output.

References
==========
`Intel Agilex Transceiver-SoC Development Kit <https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-agf-si.html>`_

Part 3

한국어 전문 번역

개요

Intel Agilex SoC Development Kit는 Intel Agilex F-Series FPGA design 개발에 필요한 hardware와 software를 포함한 complete design environment를 제공합니다. Custom Arm processor 기반 SoC design 개발과 transceiver performance 평가에 권장됩니다.

Hardware

  • 1400KLE, 2486A package와 quad-core Arm Cortex-A53 processor를 통합한 Intel Agilex F-Series FPGA
  • Onboard 8GB DDR4 memory
  • Onboard JTAG Intel FPGA Download Cable II
  • QSPI flash daughtercard
  • UART와 SD card를 지원하는 HPS OOBE daughtercard

지원 기능

InterfaceControllerDriver/Component
GIC-400on-chipGICv2 interrupt controller
ARM TIMERon-chipSystem Clock
UARTon-chipNS16550 compatible serial port

그 밖의 hardware 기능은 아직 이 board에서 활성화되지 않았습니다. Default configuration은 boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig에 있습니다.

Programming과 Debugging

Boot flow

Zephyr image는 Intel Arm Trusted Firmware(ATF)가 load해야 합니다. ATF BL2는 first-stage boot loader(FSBL), ATF BL31은 second-stage boot loader(SSBL)입니다.

ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1)

Intel ATF는 altera-opensource/arm-trusted-firmware에서 받을 수 있습니다.

Flashing

ATF BL2가 SD card 또는 QSPI flash에서 Zephyr image를 DDR address 0x10000000에 load할 수 있습니다.

Debugging

Board의 JTAG connector를 Intel USB Blaster download cable에 연결해 debug합니다. Cortex-A53 core에서 실행되는 Zephyr application은 UART console output으로 시험할 수 있습니다.

참고 자료

Intel Agilex Transceiver-SoC Development Kit

Source

출처

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