개념 설명 전체 · v6.18.37 / arch/riscv/include/asm/pgtable.h
1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #ifdef CONFIG_RELOCATABLE 16 #define KERNEL_LINK_ADDR UL(0) 17 #else 18 #define KERNEL_LINK_ADDR _AC(CONFIG_PHYS_RAM_BASE, UL) 19 #endif 20 #define KERN_VIRT_SIZE (UL(-1)) 21 #else 22 23 #define ADDRESS_SPACE_END (UL(-1)) 24 25 #ifdef CONFIG_64BIT 26 /* Leave 2GB for kernel and BPF at the end of the address space */ 27 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 28 #else 29 #define KERNEL_LINK_ADDR PAGE_OFFSET 30 #endif 31 32 /* Number of entries in the page global directory */ 33 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 34 /* Number of entries in the page table */ 35 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 36 37 /* 38 * Half of the kernel address space (1/4 of the entries of the page global 39 * directory) is for the direct mapping. 40 */ 41 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 42 43 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 44 #define VMALLOC_END PAGE_OFFSET 45 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 46 47 #define BPF_JIT_REGION_SIZE (SZ_128M) 48 #ifdef CONFIG_64BIT 49 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 50 #define BPF_JIT_REGION_END (MODULES_END) 51 #else 52 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 53 #define BPF_JIT_REGION_END (VMALLOC_END) 54 #endif 55 56 /* Modules always live before the kernel */ 57 #ifdef CONFIG_64BIT 58 /* This is used to define the end of the KASAN shadow region */ 59 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 60 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 61 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 62 #else 63 #define MODULES_VADDR VMALLOC_START 64 #define MODULES_END VMALLOC_END 65 #endif 66 67 /* 68 * Roughly size the vmemmap space to be large enough to fit enough 69 * struct pages to map half the virtual address space. Then 70 * position vmemmap directly below the VMALLOC region. 71 */ 72 #define VA_BITS_SV32 32 73 #ifdef CONFIG_64BIT 74 #define VA_BITS_SV39 39 75 #define VA_BITS_SV48 48 76 #define VA_BITS_SV57 57 77 78 #define VA_BITS (pgtable_l5_enabled ? \ 79 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) 80 #else 81 #define VA_BITS VA_BITS_SV32 82 #endif 83 84 #define VMEMMAP_SHIFT \ 85 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 86 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 87 #define VMEMMAP_END VMALLOC_START 88 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 89 90 /* 91 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 92 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 93 */ 94 #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) 95 96 #define PCI_IO_SIZE SZ_16M 97 #define PCI_IO_END VMEMMAP_START 98 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 99 100 #define FIXADDR_TOP PCI_IO_START 101 #ifdef CONFIG_64BIT 102 #define MAX_FDT_SIZE PMD_SIZE 103 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 104 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 105 #else 106 #define MAX_FDT_SIZE PGDIR_SIZE 107 #define FIX_FDT_SIZE MAX_FDT_SIZE 108 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 109 #endif 110 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 111 112 #endif 113 114 #ifndef __ASSEMBLER__ 115 116 #include <asm/page.h> 117 #include <asm/tlbflush.h> 118 #include <linux/mm_types.h> 119 #include <asm/compat.h> 120 #include <asm/cpufeature.h> 121 122 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 123 124 #ifdef CONFIG_64BIT 125 #include <asm/pgtable-64.h> 126 127 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 128 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39) 129 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64) 130 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64) 131 #else 132 #include <asm/pgtable-32.h> 133 #endif /* CONFIG_64BIT */ 134 135 #include <linux/page_table_check.h> 136 137 #ifdef CONFIG_XIP_KERNEL 138 #define XIP_FIXUP(addr) ({ \ 139 extern char _sdata[], _start[], _end[]; \ 140 uintptr_t __rom_start_data = CONFIG_XIP_PHYS_ADDR \ 141 + (uintptr_t)&_sdata - (uintptr_t)&_start; \ 142 uintptr_t __rom_end_data = CONFIG_XIP_PHYS_ADDR \ 143 + (uintptr_t)&_end - (uintptr_t)&_start; \ 144 uintptr_t __a = (uintptr_t)(addr); \ 145 (__a >= __rom_start_data && __a < __rom_end_data) ? \ 146 __a - __rom_start_data + CONFIG_PHYS_RAM_BASE : __a; \ 147 }) 148 #else 149 #define XIP_FIXUP(addr) (addr) 150 #endif /* CONFIG_XIP_KERNEL */ 151 152 struct pt_alloc_ops { 153 pte_t *(*get_pte_virt)(phys_addr_t pa); 154 phys_addr_t (*alloc_pte)(uintptr_t va); 155 #ifndef __PAGETABLE_PMD_FOLDED 156 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 157 phys_addr_t (*alloc_pmd)(uintptr_t va); 158 pud_t *(*get_pud_virt)(phys_addr_t pa); 159 phys_addr_t (*alloc_pud)(uintptr_t va); 160 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 161 phys_addr_t (*alloc_p4d)(uintptr_t va); 162 #endif 163 }; 164 165 extern struct pt_alloc_ops pt_ops __meminitdata; 166 167 #ifdef CONFIG_MMU 168 /* Number of PGD entries that a user-mode program can use */ 169 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 170 171 /* Page protection bits */ 172 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 173 174 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 175 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 176 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 177 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 178 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 179 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 180 _PAGE_EXEC | _PAGE_WRITE) 181 182 #define PAGE_COPY PAGE_READ 183 #define PAGE_COPY_EXEC PAGE_READ_EXEC 184 #define PAGE_SHARED PAGE_WRITE 185 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 186 187 #define _PAGE_KERNEL (_PAGE_READ \ 188 | _PAGE_WRITE \ 189 | _PAGE_PRESENT \ 190 | _PAGE_ACCESSED \ 191 | _PAGE_DIRTY \ 192 | _PAGE_GLOBAL) 193 194 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 195 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 196 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 197 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 198 | _PAGE_EXEC) 199 200 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 201 202 #define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) 203 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 204 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 205 206 extern pgd_t swapper_pg_dir[]; 207 extern pgd_t trampoline_pg_dir[]; 208 extern pgd_t early_pg_dir[]; 209 210 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 211 static inline int pmd_present(pmd_t pmd) 212 { 213 /* 214 * Checking for _PAGE_LEAF is needed too because: 215 * When splitting a THP, split_huge_page() will temporarily clear 216 * the present bit, in this situation, pmd_present() and 217 * pmd_trans_huge() still needs to return true. 218 */ 219 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 220 } 221 #else 222 static inline int pmd_present(pmd_t pmd) 223 { 224 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 225 } 226 #endif 227 228 static inline int pmd_none(pmd_t pmd) 229 { 230 return (pmd_val(pmd) == 0); 231 } 232 233 static inline int pmd_bad(pmd_t pmd) 234 { 235 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 236 } 237 238 #define pmd_leaf pmd_leaf 239 static inline bool pmd_leaf(pmd_t pmd) 240 { 241 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 242 } 243 244 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 245 { 246 WRITE_ONCE(*pmdp, pmd); 247 } 248 249 static inline void pmd_clear(pmd_t *pmdp) 250 { 251 set_pmd(pmdp, __pmd(0)); 252 } 253 254 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 255 { 256 unsigned long prot_val = pgprot_val(prot); 257 258 ALT_THEAD_PMA(prot_val); 259 260 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 261 } 262 263 static inline unsigned long _pgd_pfn(pgd_t pgd) 264 { 265 return __page_val_to_pfn(pgd_val(pgd)); 266 } 267 268 static inline struct page *pmd_page(pmd_t pmd) 269 { 270 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 271 } 272 273 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 274 { 275 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 276 } 277 278 static inline pte_t pmd_pte(pmd_t pmd) 279 { 280 return __pte(pmd_val(pmd)); 281 } 282 283 static inline pte_t pud_pte(pud_t pud) 284 { 285 return __pte(pud_val(pud)); 286 } 287 288 #ifdef CONFIG_RISCV_ISA_SVNAPOT 289 290 static __always_inline bool has_svnapot(void) 291 { 292 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 293 } 294 295 static inline unsigned long pte_napot(pte_t pte) 296 { 297 return pte_val(pte) & _PAGE_NAPOT; 298 } 299 300 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 301 { 302 int pos = order - 1 + _PAGE_PFN_SHIFT; 303 unsigned long napot_bit = BIT(pos); 304 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 305 306 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 307 } 308 309 #else 310 311 static __always_inline bool has_svnapot(void) { return false; } 312 313 static inline unsigned long pte_napot(pte_t pte) 314 { 315 return 0; 316 } 317 318 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 319 320 /* Yields the page frame number (PFN) of a page table entry */ 321 static inline unsigned long pte_pfn(pte_t pte) 322 { 323 unsigned long res = __page_val_to_pfn(pte_val(pte)); 324 325 if (has_svnapot() && pte_napot(pte)) 326 res = res & (res - 1UL); 327 328 return res; 329 } 330 331 #define pte_page(x) pfn_to_page(pte_pfn(x)) 332 333 /* Constructs a page table entry */ 334 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 335 { 336 unsigned long prot_val = pgprot_val(prot); 337 338 ALT_THEAD_PMA(prot_val); 339 340 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 341 } 342 343 #define pte_pgprot pte_pgprot 344 static inline pgprot_t pte_pgprot(pte_t pte) 345 { 346 unsigned long pfn = pte_pfn(pte); 347 348 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 349 } 350 351 static inline int pte_present(pte_t pte) 352 { 353 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 354 } 355 356 #define pte_accessible pte_accessible 357 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 358 { 359 if (pte_val(a) & _PAGE_PRESENT) 360 return true; 361 362 if ((pte_val(a) & _PAGE_PROT_NONE) && 363 atomic_read(&mm->tlb_flush_pending)) 364 return true; 365 366 return false; 367 } 368 369 static inline int pte_none(pte_t pte) 370 { 371 return (pte_val(pte) == 0); 372 } 373 374 static inline int pte_write(pte_t pte) 375 { 376 return pte_val(pte) & _PAGE_WRITE; 377 } 378 379 static inline int pte_exec(pte_t pte) 380 { 381 return pte_val(pte) & _PAGE_EXEC; 382 } 383 384 static inline int pte_user(pte_t pte) 385 { 386 return pte_val(pte) & _PAGE_USER; 387 } 388 389 static inline int pte_huge(pte_t pte) 390 { 391 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 392 } 393 394 static inline int pte_dirty(pte_t pte) 395 { 396 return pte_val(pte) & _PAGE_DIRTY; 397 } 398 399 static inline int pte_young(pte_t pte) 400 { 401 return pte_val(pte) & _PAGE_ACCESSED; 402 } 403 404 static inline int pte_special(pte_t pte) 405 { 406 return pte_val(pte) & _PAGE_SPECIAL; 407 } 408 409 /* static inline pte_t pte_rdprotect(pte_t pte) */ 410 411 static inline pte_t pte_wrprotect(pte_t pte) 412 { 413 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 414 } 415 416 /* static inline pte_t pte_mkread(pte_t pte) */ 417 418 static inline pte_t pte_mkwrite_novma(pte_t pte) 419 { 420 return __pte(pte_val(pte) | _PAGE_WRITE); 421 } 422 423 /* static inline pte_t pte_mkexec(pte_t pte) */ 424 425 static inline pte_t pte_mkdirty(pte_t pte) 426 { 427 return __pte(pte_val(pte) | _PAGE_DIRTY); 428 } 429 430 static inline pte_t pte_mkclean(pte_t pte) 431 { 432 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 433 } 434 435 static inline pte_t pte_mkyoung(pte_t pte) 436 { 437 return __pte(pte_val(pte) | _PAGE_ACCESSED); 438 } 439 440 static inline pte_t pte_mkold(pte_t pte) 441 { 442 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 443 } 444 445 static inline pte_t pte_mkspecial(pte_t pte) 446 { 447 return __pte(pte_val(pte) | _PAGE_SPECIAL); 448 } 449 450 static inline pte_t pte_mkhuge(pte_t pte) 451 { 452 return pte; 453 } 454 455 #ifdef CONFIG_RISCV_ISA_SVNAPOT 456 #define pte_leaf_size(pte) (pte_napot(pte) ? \ 457 napot_cont_size(napot_cont_order(pte)) :\ 458 PAGE_SIZE) 459 #endif 460 461 #ifdef CONFIG_NUMA_BALANCING 462 /* 463 * See the comment in include/asm-generic/pgtable.h 464 */ 465 static inline int pte_protnone(pte_t pte) 466 { 467 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 468 } 469 470 static inline int pmd_protnone(pmd_t pmd) 471 { 472 return pte_protnone(pmd_pte(pmd)); 473 } 474 #endif 475 476 /* Modify page protection bits */ 477 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 478 { 479 unsigned long newprot_val = pgprot_val(newprot); 480 481 ALT_THEAD_PMA(newprot_val); 482 483 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 484 } 485 486 #define pgd_ERROR(e) \ 487 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 488 489 490 /* Commit new configuration to MMU hardware */ 491 static inline void update_mmu_cache_range(struct vm_fault *vmf, 492 struct vm_area_struct *vma, unsigned long address, 493 pte_t *ptep, unsigned int nr) 494 { 495 asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) 496 : : : : svvptc); 497 498 /* 499 * The kernel assumes that TLBs don't cache invalid entries, but 500 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 501 * cache flush; it is necessary even after writing invalid entries. 502 * Relying on flush_tlb_fix_spurious_fault would suffice, but 503 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 504 */ 505 while (nr--) 506 local_flush_tlb_page(address + nr * PAGE_SIZE); 507 508 svvptc:; 509 /* 510 * Svvptc guarantees that the new valid pte will be visible within 511 * a bounded timeframe, so when the uarch does not cache invalid 512 * entries, we don't have to do anything. 513 */ 514 } 515 #define update_mmu_cache(vma, addr, ptep) \ 516 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 517 518 #define update_mmu_tlb_range(vma, addr, ptep, nr) \ 519 update_mmu_cache_range(NULL, vma, addr, ptep, nr) 520 521 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 522 unsigned long address, pmd_t *pmdp) 523 { 524 pte_t *ptep = (pte_t *)pmdp; 525 526 update_mmu_cache(vma, address, ptep); 527 } 528 529 #define __HAVE_ARCH_PTE_SAME 530 static inline int pte_same(pte_t pte_a, pte_t pte_b) 531 { 532 return pte_val(pte_a) == pte_val(pte_b); 533 } 534 535 /* 536 * Certain architectures need to do special things when PTEs within 537 * a page table are directly modified. Thus, the following hook is 538 * made available. 539 */ 540 static inline void set_pte(pte_t *ptep, pte_t pteval) 541 { 542 WRITE_ONCE(*ptep, pteval); 543 } 544 545 void flush_icache_pte(struct mm_struct *mm, pte_t pte); 546 547 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval) 548 { 549 if (pte_present(pteval) && pte_exec(pteval)) 550 flush_icache_pte(mm, pteval); 551 552 set_pte(ptep, pteval); 553 } 554 555 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT 556 557 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 558 pte_t *ptep, pte_t pteval, unsigned int nr) 559 { 560 page_table_check_ptes_set(mm, ptep, pteval, nr); 561 562 for (;;) { 563 __set_pte_at(mm, ptep, pteval); 564 if (--nr == 0) 565 break; 566 ptep++; 567 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; 568 } 569 } 570 #define set_ptes set_ptes 571 572 static inline void pte_clear(struct mm_struct *mm, 573 unsigned long addr, pte_t *ptep) 574 { 575 __set_pte_at(mm, ptep, __pte(0)); 576 } 577 578 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */ 579 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 580 pte_t *ptep, pte_t entry, int dirty); 581 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */ 582 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address, 583 pte_t *ptep); 584 585 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 586 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 587 unsigned long address, pte_t *ptep) 588 { 589 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 590 591 page_table_check_pte_clear(mm, pte); 592 593 return pte; 594 } 595 596 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 597 static inline void ptep_set_wrprotect(struct mm_struct *mm, 598 unsigned long address, pte_t *ptep) 599 { 600 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 601 } 602 603 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 604 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 605 unsigned long address, pte_t *ptep) 606 { 607 /* 608 * This comment is borrowed from x86, but applies equally to RISC-V: 609 * 610 * Clearing the accessed bit without a TLB flush 611 * doesn't cause data corruption. [ It could cause incorrect 612 * page aging and the (mistaken) reclaim of hot pages, but the 613 * chance of that should be relatively low. ] 614 * 615 * So as a performance optimization don't flush the TLB when 616 * clearing the accessed bit, it will eventually be flushed by 617 * a context switch or a VM operation anyway. [ In the rare 618 * event of it not getting flushed for a long time the delay 619 * shouldn't really matter because there's no real memory 620 * pressure for swapout to react to. ] 621 */ 622 return ptep_test_and_clear_young(vma, address, ptep); 623 } 624 625 #define pgprot_nx pgprot_nx 626 static inline pgprot_t pgprot_nx(pgprot_t _prot) 627 { 628 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC); 629 } 630 631 #define pgprot_noncached pgprot_noncached 632 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 633 { 634 unsigned long prot = pgprot_val(_prot); 635 636 prot &= ~_PAGE_MTMASK; 637 prot |= _PAGE_IO; 638 639 return __pgprot(prot); 640 } 641 642 #define pgprot_writecombine pgprot_writecombine 643 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 644 { 645 unsigned long prot = pgprot_val(_prot); 646 647 prot &= ~_PAGE_MTMASK; 648 prot |= _PAGE_NOCACHE; 649 650 return __pgprot(prot); 651 } 652 653 #define pgprot_dmacoherent pgprot_writecombine 654 655 /* 656 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By 657 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in 658 * DT. 659 */ 660 #define arch_has_hw_pte_young arch_has_hw_pte_young 661 static inline bool arch_has_hw_pte_young(void) 662 { 663 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); 664 } 665 666 /* 667 * THP functions 668 */ 669 static inline pmd_t pte_pmd(pte_t pte) 670 { 671 return __pmd(pte_val(pte)); 672 } 673 674 static inline pud_t pte_pud(pte_t pte) 675 { 676 return __pud(pte_val(pte)); 677 } 678 679 static inline pmd_t pmd_mkhuge(pmd_t pmd) 680 { 681 return pmd; 682 } 683 684 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 685 { 686 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 687 } 688 689 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 690 691 static inline unsigned long pmd_pfn(pmd_t pmd) 692 { 693 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 694 } 695 696 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 697 698 #define pud_pfn pud_pfn 699 static inline unsigned long pud_pfn(pud_t pud) 700 { 701 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 702 } 703 704 #define pmd_pgprot pmd_pgprot 705 static inline pgprot_t pmd_pgprot(pmd_t pmd) 706 { 707 return pte_pgprot(pmd_pte(pmd)); 708 } 709 710 #define pud_pgprot pud_pgprot 711 static inline pgprot_t pud_pgprot(pud_t pud) 712 { 713 return pte_pgprot(pud_pte(pud)); 714 } 715 716 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 717 { 718 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 719 } 720 721 #define pmd_write pmd_write 722 static inline int pmd_write(pmd_t pmd) 723 { 724 return pte_write(pmd_pte(pmd)); 725 } 726 727 #define pud_write pud_write 728 static inline int pud_write(pud_t pud) 729 { 730 return pte_write(pud_pte(pud)); 731 } 732 733 #define pmd_dirty pmd_dirty 734 static inline int pmd_dirty(pmd_t pmd) 735 { 736 return pte_dirty(pmd_pte(pmd)); 737 } 738 739 #define pmd_young pmd_young 740 static inline int pmd_young(pmd_t pmd) 741 { 742 return pte_young(pmd_pte(pmd)); 743 } 744 745 static inline int pmd_user(pmd_t pmd) 746 { 747 return pte_user(pmd_pte(pmd)); 748 } 749 750 static inline pmd_t pmd_mkold(pmd_t pmd) 751 { 752 return pte_pmd(pte_mkold(pmd_pte(pmd))); 753 } 754 755 static inline pmd_t pmd_mkyoung(pmd_t pmd) 756 { 757 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 758 } 759 760 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 761 { 762 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); 763 } 764 765 static inline pmd_t pmd_wrprotect(pmd_t pmd) 766 { 767 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 768 } 769 770 static inline pmd_t pmd_mkclean(pmd_t pmd) 771 { 772 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 773 } 774 775 static inline pmd_t pmd_mkdirty(pmd_t pmd) 776 { 777 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 778 } 779 780 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 781 static inline bool pmd_special(pmd_t pmd) 782 { 783 return pte_special(pmd_pte(pmd)); 784 } 785 786 static inline pmd_t pmd_mkspecial(pmd_t pmd) 787 { 788 return pte_pmd(pte_mkspecial(pmd_pte(pmd))); 789 } 790 #endif 791 792 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 793 static inline bool pud_special(pud_t pud) 794 { 795 return pte_special(pud_pte(pud)); 796 } 797 798 static inline pud_t pud_mkspecial(pud_t pud) 799 { 800 return pte_pud(pte_mkspecial(pud_pte(pud))); 801 } 802 #endif 803 804 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 805 pmd_t *pmdp, pmd_t pmd) 806 { 807 page_table_check_pmd_set(mm, pmdp, pmd); 808 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd)); 809 } 810 811 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 812 pud_t *pudp, pud_t pud) 813 { 814 page_table_check_pud_set(mm, pudp, pud); 815 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud)); 816 } 817 818 #ifdef CONFIG_PAGE_TABLE_CHECK 819 static inline bool pte_user_accessible_page(pte_t pte) 820 { 821 return pte_present(pte) && pte_user(pte); 822 } 823 824 static inline bool pmd_user_accessible_page(pmd_t pmd) 825 { 826 return pmd_leaf(pmd) && pmd_user(pmd); 827 } 828 829 static inline bool pud_user_accessible_page(pud_t pud) 830 { 831 return pud_leaf(pud) && pud_user(pud); 832 } 833 #endif 834 835 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 836 static inline int pmd_trans_huge(pmd_t pmd) 837 { 838 return pmd_leaf(pmd); 839 } 840 841 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 842 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 843 unsigned long address, pmd_t *pmdp, 844 pmd_t entry, int dirty) 845 { 846 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 847 } 848 849 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 850 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 851 unsigned long address, pmd_t *pmdp) 852 { 853 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 854 } 855 856 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 857 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 858 unsigned long address, pmd_t *pmdp) 859 { 860 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 861 862 page_table_check_pmd_clear(mm, pmd); 863 864 return pmd; 865 } 866 867 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 868 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 869 unsigned long address, pmd_t *pmdp) 870 { 871 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 872 } 873 874 #define pmdp_establish pmdp_establish 875 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 876 unsigned long address, pmd_t *pmdp, pmd_t pmd) 877 { 878 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 879 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 880 } 881 882 #define pmdp_collapse_flush pmdp_collapse_flush 883 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 884 unsigned long address, pmd_t *pmdp); 885 886 static inline pud_t pud_wrprotect(pud_t pud) 887 { 888 return pte_pud(pte_wrprotect(pud_pte(pud))); 889 } 890 891 static inline int pud_trans_huge(pud_t pud) 892 { 893 return pud_leaf(pud); 894 } 895 896 static inline int pud_dirty(pud_t pud) 897 { 898 return pte_dirty(pud_pte(pud)); 899 } 900 901 static inline pud_t pud_mkyoung(pud_t pud) 902 { 903 return pte_pud(pte_mkyoung(pud_pte(pud))); 904 } 905 906 static inline pud_t pud_mkold(pud_t pud) 907 { 908 return pte_pud(pte_mkold(pud_pte(pud))); 909 } 910 911 static inline pud_t pud_mkdirty(pud_t pud) 912 { 913 return pte_pud(pte_mkdirty(pud_pte(pud))); 914 } 915 916 static inline pud_t pud_mkclean(pud_t pud) 917 { 918 return pte_pud(pte_mkclean(pud_pte(pud))); 919 } 920 921 static inline pud_t pud_mkwrite(pud_t pud) 922 { 923 return pte_pud(pte_mkwrite_novma(pud_pte(pud))); 924 } 925 926 static inline pud_t pud_mkhuge(pud_t pud) 927 { 928 return pud; 929 } 930 931 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 932 unsigned long address, pud_t *pudp, 933 pud_t entry, int dirty) 934 { 935 return ptep_set_access_flags(vma, address, (pte_t *)pudp, pud_pte(entry), dirty); 936 } 937 938 static inline int pudp_test_and_clear_young(struct vm_area_struct *vma, 939 unsigned long address, pud_t *pudp) 940 { 941 return ptep_test_and_clear_young(vma, address, (pte_t *)pudp); 942 } 943 944 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 945 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 946 unsigned long address, pud_t *pudp) 947 { 948 #ifdef CONFIG_SMP 949 pud_t pud = __pud(xchg(&pudp->pud, 0)); 950 #else 951 pud_t pud = *pudp; 952 953 pud_clear(pudp); 954 #endif 955 956 page_table_check_pud_clear(mm, pud); 957 958 return pud; 959 } 960 961 static inline int pud_young(pud_t pud) 962 { 963 return pte_young(pud_pte(pud)); 964 } 965 966 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 967 unsigned long address, pud_t *pudp) 968 { 969 pte_t *ptep = (pte_t *)pudp; 970 971 update_mmu_cache(vma, address, ptep); 972 } 973 974 static inline pud_t pudp_establish(struct vm_area_struct *vma, 975 unsigned long address, pud_t *pudp, pud_t pud) 976 { 977 page_table_check_pud_set(vma->vm_mm, pudp, pud); 978 return __pud(atomic_long_xchg((atomic_long_t *)pudp, pud_val(pud))); 979 } 980 981 static inline pud_t pud_mkinvalid(pud_t pud) 982 { 983 return __pud(pud_val(pud) & ~(_PAGE_PRESENT | _PAGE_PROT_NONE)); 984 } 985 986 extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 987 pud_t *pudp); 988 989 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot) 990 { 991 return pte_pud(pte_modify(pud_pte(pud), newprot)); 992 } 993 994 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 995 996 /* 997 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 998 * are !pte_none() && !pte_present(). 999 * 1000 * Format of swap PTE: 1001 * bit 0: _PAGE_PRESENT (zero) 1002 * bit 1 to 3: _PAGE_LEAF (zero) 1003 * bit 5: _PAGE_PROT_NONE (zero) 1004 * bit 6: exclusive marker 1005 * bits 7 to 11: swap type 1006 * bits 12 to XLEN-1: swap offset 1007 */ 1008 #define __SWP_TYPE_SHIFT 7 1009 #define __SWP_TYPE_BITS 5 1010 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 1011 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 1012 1013 #define MAX_SWAPFILES_CHECK() \ 1014 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1015 1016 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1017 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 1018 #define __swp_entry(type, offset) ((swp_entry_t) \ 1019 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 1020 ((offset) << __SWP_OFFSET_SHIFT) }) 1021 1022 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1023 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1024 1025 static inline bool pte_swp_exclusive(pte_t pte) 1026 { 1027 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 1028 } 1029 1030 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1031 { 1032 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 1033 } 1034 1035 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1036 { 1037 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 1038 } 1039 1040 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1041 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1042 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1043 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1044 1045 /* 1046 * In the RV64 Linux scheme, we give the user half of the virtual-address space 1047 * and give the kernel the other (upper) half. 1048 */ 1049 #ifdef CONFIG_64BIT 1050 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 1051 #else 1052 #define KERN_VIRT_START FIXADDR_START 1053 #endif 1054 1055 /* 1056 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 1057 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 1058 * Task size is: 1059 * - 0x9fc00000 (~2.5GB) for RV32. 1060 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 1061 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 1062 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu 1063 * 1064 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 1065 * Instruction Set Manual Volume II: Privileged Architecture" states that 1066 * "load and store effective addresses, which are 64bits, must have bits 1067 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 1068 * Similarly for SV57, bits 63–57 must be equal to bit 56. 1069 */ 1070 #ifdef CONFIG_64BIT 1071 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 1072 1073 #ifdef CONFIG_COMPAT 1074 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 1075 #define TASK_SIZE (is_compat_task() ? \ 1076 TASK_SIZE_32 : TASK_SIZE_64) 1077 #else 1078 #define TASK_SIZE TASK_SIZE_64 1079 #endif 1080 1081 #else 1082 #define TASK_SIZE FIXADDR_START 1083 #endif 1084 1085 #else /* CONFIG_MMU */ 1086 1087 #define PAGE_SHARED __pgprot(0) 1088 #define PAGE_KERNEL __pgprot(0) 1089 #define swapper_pg_dir NULL 1090 #define TASK_SIZE _AC(-1, UL) 1091 #define VMALLOC_START _AC(0, UL) 1092 #define VMALLOC_END TASK_SIZE 1093 1094 #endif /* !CONFIG_MMU */ 1095 1096 extern char _start[]; 1097 extern void *_dtb_early_va; 1098 extern uintptr_t _dtb_early_pa; 1099 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 1100 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 1101 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 1102 #else 1103 #define dtb_early_va _dtb_early_va 1104 #define dtb_early_pa _dtb_early_pa 1105 #endif /* CONFIG_XIP_KERNEL */ 1106 extern u64 satp_mode; 1107 1108 void paging_init(void); 1109 void misc_mem_init(void); 1110 1111 /* 1112 * ZERO_PAGE is a global shared page that is always zero, 1113 * used for zero-mapped memory areas, etc. 1114 */ 1115 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 1116 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 1117 1118 /* 1119 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1120 * TLB flush will be required as a result of the "set". For example, use 1121 * in scenarios where it is known ahead of time that the routine is 1122 * setting non-present entries, or re-setting an existing entry to the 1123 * same value. Otherwise, use the typical "set" helpers and flush the 1124 * TLB. 1125 */ 1126 #define set_p4d_safe(p4dp, p4d) \ 1127 ({ \ 1128 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1129 set_p4d(p4dp, p4d); \ 1130 }) 1131 1132 #define set_pgd_safe(pgdp, pgd) \ 1133 ({ \ 1134 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1135 set_pgd(pgdp, pgd); \ 1136 }) 1137 #endif /* !__ASSEMBLER__ */ 1138 1139 #endif /* _ASM_RISCV_PGTABLE_H */