개념 설명 전체 · v6.18.37 / arch/arm64/kernel/cpufeature.c
1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu.h> 88 #include <asm/mmu_context.h> 89 #include <asm/mte.h> 90 #include <asm/hypervisor.h> 91 #include <asm/processor.h> 92 #include <asm/smp.h> 93 #include <asm/sysreg.h> 94 #include <asm/traps.h> 95 #include <asm/vectors.h> 96 #include <asm/virt.h> 97 98 #include <asm/spectre.h> 99 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 100 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 101 102 #ifdef CONFIG_COMPAT 103 #define COMPAT_ELF_HWCAP_DEFAULT \ 104 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 105 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 106 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 107 COMPAT_HWCAP_LPAE) 108 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 109 unsigned int compat_elf_hwcap2 __read_mostly; 110 unsigned int compat_elf_hwcap3 __read_mostly; 111 #endif 112 113 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 114 EXPORT_SYMBOL(system_cpucaps); 115 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 116 117 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 118 119 /* 120 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 121 * ends up in the .bss section where it is initialized in early_map_kernel() 122 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 123 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 124 * may end up generating an incorrect idmap page table attributes. 125 */ 126 bool arm64_use_ng_mappings __read_mostly = false; 127 EXPORT_SYMBOL(arm64_use_ng_mappings); 128 129 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 130 131 /* 132 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 133 * support it? 134 */ 135 static bool __read_mostly allow_mismatched_32bit_el0; 136 137 /* 138 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 139 * seen at least one CPU capable of 32-bit EL0. 140 */ 141 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 142 143 /* 144 * Mask of CPUs supporting 32-bit EL0. 145 * Only valid if arm64_mismatched_32bit_el0 is enabled. 146 */ 147 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 148 149 void dump_cpu_features(void) 150 { 151 /* file-wide pr_fmt adds "CPU features: " prefix */ 152 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 153 } 154 155 #define __ARM64_MAX_POSITIVE(reg, field) \ 156 ((reg##_##field##_SIGNED ? \ 157 BIT(reg##_##field##_WIDTH - 1) : \ 158 BIT(reg##_##field##_WIDTH)) - 1) 159 160 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 161 162 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 163 .sys_reg = SYS_##reg, \ 164 .field_pos = reg##_##field##_SHIFT, \ 165 .field_width = reg##_##field##_WIDTH, \ 166 .sign = reg##_##field##_SIGNED, \ 167 .min_field_value = min_value, \ 168 .max_field_value = max_value, 169 170 /* 171 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 172 * an implicit maximum that depends on the sign-ess of the field. 173 * 174 * An unsigned field will be capped at all ones, while a signed field 175 * will be limited to the positive half only. 176 */ 177 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 178 __ARM64_CPUID_FIELDS(reg, field, \ 179 SYS_FIELD_VALUE(reg, field, min_value), \ 180 __ARM64_MAX_POSITIVE(reg, field)) 181 182 /* 183 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 184 * implicit minimal value to max_value. This should be used when 185 * matching a non-implemented property. 186 */ 187 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 188 __ARM64_CPUID_FIELDS(reg, field, \ 189 __ARM64_MIN_NEGATIVE(reg, field), \ 190 SYS_FIELD_VALUE(reg, field, max_value)) 191 192 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 193 { \ 194 .sign = SIGNED, \ 195 .visible = VISIBLE, \ 196 .strict = STRICT, \ 197 .type = TYPE, \ 198 .shift = SHIFT, \ 199 .width = WIDTH, \ 200 .safe_val = SAFE_VAL, \ 201 } 202 203 /* Define a feature with unsigned values */ 204 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 205 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 206 207 /* Define a feature with a signed value */ 208 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 209 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 210 211 #define ARM64_FTR_END \ 212 { \ 213 .width = 0, \ 214 } 215 216 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 217 218 static bool __system_matches_cap(unsigned int n); 219 220 /* 221 * NOTE: Any changes to the visibility of features should be kept in 222 * sync with the documentation of the CPU feature register ABI. 223 */ 224 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 239 ARM64_FTR_END, 240 }; 241 242 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 260 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 262 ARM64_FTR_END, 263 }; 264 265 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 273 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 278 ARM64_FTR_END, 279 }; 280 281 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 282 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 285 ARM64_FTR_END, 286 }; 287 288 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 296 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 299 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 300 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 305 ARM64_FTR_END, 306 }; 307 308 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 311 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 312 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 319 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 322 ARM64_FTR_END, 323 }; 324 325 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 328 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 329 ARM64_FTR_END, 330 }; 331 332 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 333 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 334 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 336 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 338 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 354 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 356 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 357 ARM64_FTR_END, 358 }; 359 360 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 362 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 364 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 366 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 404 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 406 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 407 ARM64_FTR_END, 408 }; 409 410 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 419 ARM64_FTR_END, 420 }; 421 422 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 426 /* 427 * Page size not being supported at Stage-2 is not fatal. You 428 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 429 * your favourite nesting hypervisor. 430 * 431 * There is a small corner case where the hypervisor explicitly 432 * advertises a given granule size at Stage-2 (value 2) on some 433 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 434 * vCPUs. Although this is not forbidden by the architecture, it 435 * indicates that the hypervisor is being silly (or buggy). 436 * 437 * We make no effort to cope with this and pretend that if these 438 * fields are inconsistent across vCPUs, then it isn't worth 439 * trying to bring KVM up. 440 */ 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 444 /* 445 * We already refuse to boot CPUs that don't support our configured 446 * page size, so we can only detect mismatches for a page size other 447 * than the one we're currently using. Unfortunately, SoCs like this 448 * exist in the wild so, even though we don't like it, we'll have to go 449 * along with it and treat them as non-strict. 450 */ 451 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 452 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 454 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 456 /* Linux shouldn't care about secure memory */ 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 460 /* 461 * Differing PARange is fine as long as all peripherals and memory are mapped 462 * within the minimum PARange of all CPUs 463 */ 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 465 ARM64_FTR_END, 466 }; 467 468 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 483 ARM64_FTR_END, 484 }; 485 486 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 502 ARM64_FTR_END, 503 }; 504 505 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 506 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 507 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 515 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 517 ARM64_FTR_END, 518 }; 519 520 static const struct arm64_ftr_bits ftr_ctr[] = { 521 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 522 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 523 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 524 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 527 /* 528 * Linux can handle differing I-cache policies. Userspace JITs will 529 * make use of *minLine. 530 * If we have differing I-cache policies, report it as the weakest - VIPT. 531 */ 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 534 ARM64_FTR_END, 535 }; 536 537 static struct arm64_ftr_override __ro_after_init no_override = { }; 538 539 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 540 .name = "SYS_CTR_EL0", 541 .ftr_bits = ftr_ctr, 542 .override = &no_override, 543 }; 544 545 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 546 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 551 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 554 ARM64_FTR_END, 555 }; 556 557 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 558 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 563 /* 564 * We can instantiate multiple PMU instances with different levels 565 * of support. 566 */ 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 569 ARM64_FTR_END, 570 }; 571 572 static const struct arm64_ftr_bits ftr_mvfr0[] = { 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 581 ARM64_FTR_END, 582 }; 583 584 static const struct arm64_ftr_bits ftr_mvfr1[] = { 585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 590 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 593 ARM64_FTR_END, 594 }; 595 596 static const struct arm64_ftr_bits ftr_mvfr2[] = { 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 599 ARM64_FTR_END, 600 }; 601 602 static const struct arm64_ftr_bits ftr_dczid[] = { 603 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 604 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 605 ARM64_FTR_END, 606 }; 607 608 static const struct arm64_ftr_bits ftr_gmid[] = { 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 610 ARM64_FTR_END, 611 }; 612 613 static const struct arm64_ftr_bits ftr_id_isar0[] = { 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 621 ARM64_FTR_END, 622 }; 623 624 static const struct arm64_ftr_bits ftr_id_isar5[] = { 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 631 ARM64_FTR_END, 632 }; 633 634 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 642 643 /* 644 * SpecSEI = 1 indicates that the PE might generate an SError on an 645 * external abort on speculative read. It is safe to assume that an 646 * SError might be generated than it will not be. Hence it has been 647 * classified as FTR_HIGHER_SAFE. 648 */ 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 650 ARM64_FTR_END, 651 }; 652 653 static const struct arm64_ftr_bits ftr_id_isar4[] = { 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 662 ARM64_FTR_END, 663 }; 664 665 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 667 ARM64_FTR_END, 668 }; 669 670 static const struct arm64_ftr_bits ftr_id_isar6[] = { 671 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 673 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 674 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 675 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 678 ARM64_FTR_END, 679 }; 680 681 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 688 ARM64_FTR_END, 689 }; 690 691 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 700 ARM64_FTR_END, 701 }; 702 703 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 704 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 706 ARM64_FTR_END, 707 }; 708 709 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 710 /* [31:28] TraceFilt */ 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 715 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 716 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 717 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 718 ARM64_FTR_END, 719 }; 720 721 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 722 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 723 ARM64_FTR_END, 724 }; 725 726 static const struct arm64_ftr_bits ftr_mpamidr[] = { 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 730 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 731 ARM64_FTR_END, 732 }; 733 734 /* 735 * Common ftr bits for a 32bit register with all hidden, strict 736 * attributes, with 4bit feature fields and a default safe value of 737 * 0. Covers the following 32bit registers: 738 * id_isar[1-3], id_mmfr[1-3] 739 */ 740 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 743 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 744 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 745 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 746 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 747 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 748 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 749 ARM64_FTR_END, 750 }; 751 752 /* Table for a single 32bit feature value */ 753 static const struct arm64_ftr_bits ftr_single32[] = { 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 755 ARM64_FTR_END, 756 }; 757 758 static const struct arm64_ftr_bits ftr_raz[] = { 759 ARM64_FTR_END, 760 }; 761 762 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 763 .sys_id = id, \ 764 .reg = &(struct arm64_ftr_reg){ \ 765 .name = id_str, \ 766 .override = (ovr), \ 767 .ftr_bits = &((table)[0]), \ 768 }} 769 770 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 771 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 772 773 #define ARM64_FTR_REG(id, table) \ 774 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 775 776 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 777 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 778 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 779 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 780 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 781 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 782 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 783 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 784 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 785 786 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 787 788 static const struct __ftr_reg_entry { 789 u32 sys_id; 790 struct arm64_ftr_reg *reg; 791 } arm64_ftr_regs[] = { 792 793 /* Op1 = 0, CRn = 0, CRm = 1 */ 794 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 795 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 796 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 797 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 798 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 799 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 800 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 801 802 /* Op1 = 0, CRn = 0, CRm = 2 */ 803 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 804 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 805 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 806 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 807 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 808 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 809 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 810 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 811 812 /* Op1 = 0, CRn = 0, CRm = 3 */ 813 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 814 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 815 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 816 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 817 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 818 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 819 820 /* Op1 = 0, CRn = 0, CRm = 4 */ 821 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 822 &id_aa64pfr0_override), 823 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 824 &id_aa64pfr1_override), 825 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 826 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 827 &id_aa64zfr0_override), 828 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 829 &id_aa64smfr0_override), 830 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 831 832 /* Op1 = 0, CRn = 0, CRm = 5 */ 833 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 834 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 835 836 /* Op1 = 0, CRn = 0, CRm = 6 */ 837 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 838 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 839 &id_aa64isar1_override), 840 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 841 &id_aa64isar2_override), 842 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 843 844 /* Op1 = 0, CRn = 0, CRm = 7 */ 845 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 846 &id_aa64mmfr0_override), 847 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 848 &id_aa64mmfr1_override), 849 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 850 &id_aa64mmfr2_override), 851 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 852 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 853 854 /* Op1 = 0, CRn = 10, CRm = 4 */ 855 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 856 857 /* Op1 = 1, CRn = 0, CRm = 0 */ 858 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 859 860 /* Op1 = 3, CRn = 0, CRm = 0 */ 861 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 862 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 863 864 /* Op1 = 3, CRn = 14, CRm = 0 */ 865 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 866 }; 867 868 static int search_cmp_ftr_reg(const void *id, const void *regp) 869 { 870 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 871 } 872 873 /* 874 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 875 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 876 * ascending order of sys_id, we use binary search to find a matching 877 * entry. 878 * 879 * returns - Upon success, matching ftr_reg entry for id. 880 * - NULL on failure. It is upto the caller to decide 881 * the impact of a failure. 882 */ 883 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 884 { 885 const struct __ftr_reg_entry *ret; 886 887 ret = bsearch((const void *)(unsigned long)sys_id, 888 arm64_ftr_regs, 889 ARRAY_SIZE(arm64_ftr_regs), 890 sizeof(arm64_ftr_regs[0]), 891 search_cmp_ftr_reg); 892 if (ret) 893 return ret->reg; 894 return NULL; 895 } 896 897 /* 898 * get_arm64_ftr_reg - Looks up a feature register entry using 899 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 900 * 901 * returns - Upon success, matching ftr_reg entry for id. 902 * - NULL on failure but with an WARN_ON(). 903 */ 904 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 905 { 906 struct arm64_ftr_reg *reg; 907 908 reg = get_arm64_ftr_reg_nowarn(sys_id); 909 910 /* 911 * Requesting a non-existent register search is an error. Warn 912 * and let the caller handle it. 913 */ 914 WARN_ON(!reg); 915 return reg; 916 } 917 918 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 919 s64 ftr_val) 920 { 921 u64 mask = arm64_ftr_mask(ftrp); 922 923 reg &= ~mask; 924 reg |= (ftr_val << ftrp->shift) & mask; 925 return reg; 926 } 927 928 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 929 s64 cur) 930 { 931 s64 ret = 0; 932 933 switch (ftrp->type) { 934 case FTR_EXACT: 935 ret = ftrp->safe_val; 936 break; 937 case FTR_LOWER_SAFE: 938 ret = min(new, cur); 939 break; 940 case FTR_HIGHER_OR_ZERO_SAFE: 941 if (!cur || !new) 942 break; 943 fallthrough; 944 case FTR_HIGHER_SAFE: 945 ret = max(new, cur); 946 break; 947 default: 948 BUG(); 949 } 950 951 return ret; 952 } 953 954 static void __init sort_ftr_regs(void) 955 { 956 unsigned int i; 957 958 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 959 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 960 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 961 unsigned int j = 0; 962 963 /* 964 * Features here must be sorted in descending order with respect 965 * to their shift values and should not overlap with each other. 966 */ 967 for (; ftr_bits->width != 0; ftr_bits++, j++) { 968 unsigned int width = ftr_reg->ftr_bits[j].width; 969 unsigned int shift = ftr_reg->ftr_bits[j].shift; 970 unsigned int prev_shift; 971 972 WARN((shift + width) > 64, 973 "%s has invalid feature at shift %d\n", 974 ftr_reg->name, shift); 975 976 /* 977 * Skip the first feature. There is nothing to 978 * compare against for now. 979 */ 980 if (j == 0) 981 continue; 982 983 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 984 WARN((shift + width) > prev_shift, 985 "%s has feature overlap at shift %d\n", 986 ftr_reg->name, shift); 987 } 988 989 /* 990 * Skip the first register. There is nothing to 991 * compare against for now. 992 */ 993 if (i == 0) 994 continue; 995 /* 996 * Registers here must be sorted in ascending order with respect 997 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 998 * to work correctly. 999 */ 1000 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1001 } 1002 } 1003 1004 /* 1005 * Initialise the CPU feature register from Boot CPU values. 1006 * Also initiliases the strict_mask for the register. 1007 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1008 * RES0 for the system-wide value, and must strictly match. 1009 */ 1010 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1011 { 1012 u64 val = 0; 1013 u64 strict_mask = ~0x0ULL; 1014 u64 user_mask = 0; 1015 u64 valid_mask = 0; 1016 1017 const struct arm64_ftr_bits *ftrp; 1018 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1019 1020 if (!reg) 1021 return; 1022 1023 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1024 u64 ftr_mask = arm64_ftr_mask(ftrp); 1025 s64 ftr_new = arm64_ftr_value(ftrp, new); 1026 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1027 1028 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1029 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1030 char *str = NULL; 1031 1032 if (ftr_ovr != tmp) { 1033 /* Unsafe, remove the override */ 1034 reg->override->mask &= ~ftr_mask; 1035 reg->override->val &= ~ftr_mask; 1036 tmp = ftr_ovr; 1037 str = "ignoring override"; 1038 } else if (ftr_new != tmp) { 1039 /* Override was valid */ 1040 ftr_new = tmp; 1041 str = "forced"; 1042 } else { 1043 /* Override was the safe value */ 1044 str = "already set"; 1045 } 1046 1047 pr_warn("%s[%d:%d]: %s to %llx\n", 1048 reg->name, 1049 ftrp->shift + ftrp->width - 1, 1050 ftrp->shift, str, 1051 tmp & (BIT(ftrp->width) - 1)); 1052 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1053 reg->override->val &= ~ftr_mask; 1054 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1055 reg->name, 1056 ftrp->shift + ftrp->width - 1, 1057 ftrp->shift); 1058 } 1059 1060 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1061 1062 valid_mask |= ftr_mask; 1063 if (!ftrp->strict) 1064 strict_mask &= ~ftr_mask; 1065 if (ftrp->visible) 1066 user_mask |= ftr_mask; 1067 else 1068 reg->user_val = arm64_ftr_set_value(ftrp, 1069 reg->user_val, 1070 ftrp->safe_val); 1071 } 1072 1073 val &= valid_mask; 1074 1075 reg->sys_val = val; 1076 reg->strict_mask = strict_mask; 1077 reg->user_mask = user_mask; 1078 } 1079 1080 extern const struct arm64_cpu_capabilities arm64_errata[]; 1081 static const struct arm64_cpu_capabilities arm64_features[]; 1082 1083 static void __init 1084 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1085 { 1086 for (; caps->matches; caps++) { 1087 if (WARN(caps->capability >= ARM64_NCAPS, 1088 "Invalid capability %d\n", caps->capability)) 1089 continue; 1090 if (WARN(cpucap_ptrs[caps->capability], 1091 "Duplicate entry for capability %d\n", 1092 caps->capability)) 1093 continue; 1094 cpucap_ptrs[caps->capability] = caps; 1095 } 1096 } 1097 1098 static void __init init_cpucap_indirect_list(void) 1099 { 1100 init_cpucap_indirect_list_from_array(arm64_features); 1101 init_cpucap_indirect_list_from_array(arm64_errata); 1102 } 1103 1104 static void __init setup_boot_cpu_capabilities(void); 1105 1106 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1107 { 1108 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1109 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1110 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1111 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1112 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1113 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1114 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1115 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1116 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1117 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1118 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1119 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1120 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1121 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1122 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1123 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1124 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1125 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1126 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1127 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1128 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1129 } 1130 1131 #ifdef CONFIG_ARM64_PSEUDO_NMI 1132 static bool enable_pseudo_nmi; 1133 1134 static int __init early_enable_pseudo_nmi(char *p) 1135 { 1136 return kstrtobool(p, &enable_pseudo_nmi); 1137 } 1138 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1139 1140 static __init void detect_system_supports_pseudo_nmi(void) 1141 { 1142 struct device_node *np; 1143 1144 if (!enable_pseudo_nmi) 1145 return; 1146 1147 /* 1148 * Detect broken MediaTek firmware that doesn't properly save and 1149 * restore GIC priorities. 1150 */ 1151 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1152 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1153 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1154 enable_pseudo_nmi = false; 1155 } 1156 of_node_put(np); 1157 } 1158 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1159 static inline void detect_system_supports_pseudo_nmi(void) { } 1160 #endif 1161 1162 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1163 { 1164 /* Before we start using the tables, make sure it is sorted */ 1165 sort_ftr_regs(); 1166 1167 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1168 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1169 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1170 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1171 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1172 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1173 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1174 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1175 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1176 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1177 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1178 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1179 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1180 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1181 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1182 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1183 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1184 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1185 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1186 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1187 1188 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1189 init_32bit_cpu_features(&info->aarch32); 1190 1191 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1192 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1193 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1194 1195 vec_init_vq_map(ARM64_VEC_SVE); 1196 1197 cpacr_restore(cpacr); 1198 } 1199 1200 if (IS_ENABLED(CONFIG_ARM64_SME) && 1201 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1202 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1203 1204 vec_init_vq_map(ARM64_VEC_SME); 1205 1206 cpacr_restore(cpacr); 1207 } 1208 1209 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1210 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1211 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1212 } 1213 1214 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1215 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1216 } 1217 1218 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1219 { 1220 const struct arm64_ftr_bits *ftrp; 1221 1222 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1223 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1224 s64 ftr_new = arm64_ftr_value(ftrp, new); 1225 1226 if (ftr_cur == ftr_new) 1227 continue; 1228 /* Find a safe value */ 1229 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1230 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1231 } 1232 1233 } 1234 1235 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1236 { 1237 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1238 1239 if (!regp) 1240 return 0; 1241 1242 update_cpu_ftr_reg(regp, val); 1243 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1244 return 0; 1245 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1246 regp->name, boot, cpu, val); 1247 return 1; 1248 } 1249 1250 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1251 { 1252 const struct arm64_ftr_bits *ftrp; 1253 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1254 1255 if (!regp) 1256 return; 1257 1258 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1259 if (ftrp->shift == field) { 1260 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1261 break; 1262 } 1263 } 1264 1265 /* Bogus field? */ 1266 WARN_ON(!ftrp->width); 1267 } 1268 1269 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1270 struct cpuinfo_arm64 *boot) 1271 { 1272 static bool boot_cpu_32bit_regs_overridden = false; 1273 1274 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1275 return; 1276 1277 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1278 return; 1279 1280 boot->aarch32 = info->aarch32; 1281 init_32bit_cpu_features(&boot->aarch32); 1282 boot_cpu_32bit_regs_overridden = true; 1283 } 1284 1285 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1286 struct cpuinfo_32bit *boot) 1287 { 1288 int taint = 0; 1289 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1290 1291 /* 1292 * If we don't have AArch32 at EL1, then relax the strictness of 1293 * EL1-dependent register fields to avoid spurious sanity check fails. 1294 */ 1295 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1296 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1297 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1298 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1299 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1300 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1301 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1302 } 1303 1304 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1305 info->reg_id_dfr0, boot->reg_id_dfr0); 1306 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1307 info->reg_id_dfr1, boot->reg_id_dfr1); 1308 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1309 info->reg_id_isar0, boot->reg_id_isar0); 1310 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1311 info->reg_id_isar1, boot->reg_id_isar1); 1312 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1313 info->reg_id_isar2, boot->reg_id_isar2); 1314 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1315 info->reg_id_isar3, boot->reg_id_isar3); 1316 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1317 info->reg_id_isar4, boot->reg_id_isar4); 1318 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1319 info->reg_id_isar5, boot->reg_id_isar5); 1320 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1321 info->reg_id_isar6, boot->reg_id_isar6); 1322 1323 /* 1324 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1325 * ACTLR formats could differ across CPUs and therefore would have to 1326 * be trapped for virtualization anyway. 1327 */ 1328 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1329 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1330 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1331 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1332 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1333 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1334 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1335 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1336 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1337 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1338 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1339 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1340 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1341 info->reg_id_pfr0, boot->reg_id_pfr0); 1342 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1343 info->reg_id_pfr1, boot->reg_id_pfr1); 1344 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1345 info->reg_id_pfr2, boot->reg_id_pfr2); 1346 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1347 info->reg_mvfr0, boot->reg_mvfr0); 1348 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1349 info->reg_mvfr1, boot->reg_mvfr1); 1350 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1351 info->reg_mvfr2, boot->reg_mvfr2); 1352 1353 return taint; 1354 } 1355 1356 /* 1357 * Update system wide CPU feature registers with the values from a 1358 * non-boot CPU. Also performs SANITY checks to make sure that there 1359 * aren't any insane variations from that of the boot CPU. 1360 */ 1361 void update_cpu_features(int cpu, 1362 struct cpuinfo_arm64 *info, 1363 struct cpuinfo_arm64 *boot) 1364 { 1365 int taint = 0; 1366 1367 /* 1368 * The kernel can handle differing I-cache policies, but otherwise 1369 * caches should look identical. Userspace JITs will make use of 1370 * *minLine. 1371 */ 1372 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1373 info->reg_ctr, boot->reg_ctr); 1374 1375 /* 1376 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1377 * could result in too much or too little memory being zeroed if a 1378 * process is preempted and migrated between CPUs. 1379 */ 1380 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1381 info->reg_dczid, boot->reg_dczid); 1382 1383 /* If different, timekeeping will be broken (especially with KVM) */ 1384 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1385 info->reg_cntfrq, boot->reg_cntfrq); 1386 1387 /* 1388 * The kernel uses self-hosted debug features and expects CPUs to 1389 * support identical debug features. We presently need CTX_CMPs, WRPs, 1390 * and BRPs to be identical. 1391 * ID_AA64DFR1 is currently RES0. 1392 */ 1393 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1394 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1395 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1396 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1397 /* 1398 * Even in big.LITTLE, processors should be identical instruction-set 1399 * wise. 1400 */ 1401 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1402 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1403 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1404 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1405 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1406 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1407 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1408 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1409 1410 /* 1411 * Differing PARange support is fine as long as all peripherals and 1412 * memory are mapped within the minimum PARange of all CPUs. 1413 * Linux should not care about secure memory. 1414 */ 1415 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1416 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1417 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1418 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1419 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1420 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1421 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1422 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1423 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1424 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1425 1426 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1427 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1428 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1429 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1430 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1431 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1432 1433 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1434 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1435 1436 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1437 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1438 1439 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1440 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1441 1442 /* Probe vector lengths */ 1443 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1444 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1445 if (!system_capabilities_finalized()) { 1446 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1447 1448 vec_update_vq_map(ARM64_VEC_SVE); 1449 1450 cpacr_restore(cpacr); 1451 } 1452 } 1453 1454 if (IS_ENABLED(CONFIG_ARM64_SME) && 1455 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1456 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1457 1458 /* Probe vector lengths */ 1459 if (!system_capabilities_finalized()) 1460 vec_update_vq_map(ARM64_VEC_SME); 1461 1462 cpacr_restore(cpacr); 1463 } 1464 1465 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1466 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1467 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1468 info->reg_mpamidr, boot->reg_mpamidr); 1469 } 1470 1471 /* 1472 * The kernel uses the LDGM/STGM instructions and the number of tags 1473 * they read/write depends on the GMID_EL1.BS field. Check that the 1474 * value is the same on all CPUs. 1475 */ 1476 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1477 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1478 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1479 info->reg_gmid, boot->reg_gmid); 1480 } 1481 1482 /* 1483 * If we don't have AArch32 at all then skip the checks entirely 1484 * as the register values may be UNKNOWN and we're not going to be 1485 * using them for anything. 1486 * 1487 * This relies on a sanitised view of the AArch64 ID registers 1488 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1489 */ 1490 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1491 lazy_init_32bit_cpu_features(info, boot); 1492 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1493 &boot->aarch32); 1494 } 1495 1496 /* 1497 * Mismatched CPU features are a recipe for disaster. Don't even 1498 * pretend to support them. 1499 */ 1500 if (taint) { 1501 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1502 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1503 } 1504 } 1505 1506 u64 read_sanitised_ftr_reg(u32 id) 1507 { 1508 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1509 1510 if (!regp) 1511 return 0; 1512 return regp->sys_val; 1513 } 1514 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1515 1516 #define read_sysreg_case(r) \ 1517 case r: val = read_sysreg_s(r); break; 1518 1519 /* 1520 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1521 * Read the system register on the current CPU 1522 */ 1523 u64 __read_sysreg_by_encoding(u32 sys_id) 1524 { 1525 struct arm64_ftr_reg *regp; 1526 u64 val; 1527 1528 switch (sys_id) { 1529 read_sysreg_case(SYS_ID_PFR0_EL1); 1530 read_sysreg_case(SYS_ID_PFR1_EL1); 1531 read_sysreg_case(SYS_ID_PFR2_EL1); 1532 read_sysreg_case(SYS_ID_DFR0_EL1); 1533 read_sysreg_case(SYS_ID_DFR1_EL1); 1534 read_sysreg_case(SYS_ID_MMFR0_EL1); 1535 read_sysreg_case(SYS_ID_MMFR1_EL1); 1536 read_sysreg_case(SYS_ID_MMFR2_EL1); 1537 read_sysreg_case(SYS_ID_MMFR3_EL1); 1538 read_sysreg_case(SYS_ID_MMFR4_EL1); 1539 read_sysreg_case(SYS_ID_MMFR5_EL1); 1540 read_sysreg_case(SYS_ID_ISAR0_EL1); 1541 read_sysreg_case(SYS_ID_ISAR1_EL1); 1542 read_sysreg_case(SYS_ID_ISAR2_EL1); 1543 read_sysreg_case(SYS_ID_ISAR3_EL1); 1544 read_sysreg_case(SYS_ID_ISAR4_EL1); 1545 read_sysreg_case(SYS_ID_ISAR5_EL1); 1546 read_sysreg_case(SYS_ID_ISAR6_EL1); 1547 read_sysreg_case(SYS_MVFR0_EL1); 1548 read_sysreg_case(SYS_MVFR1_EL1); 1549 read_sysreg_case(SYS_MVFR2_EL1); 1550 1551 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1552 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1553 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1554 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1555 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1556 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1557 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1558 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1559 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1560 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1561 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1562 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1563 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1564 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1565 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1566 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1567 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1568 1569 read_sysreg_case(SYS_CNTFRQ_EL0); 1570 read_sysreg_case(SYS_CTR_EL0); 1571 read_sysreg_case(SYS_DCZID_EL0); 1572 1573 default: 1574 BUG(); 1575 return 0; 1576 } 1577 1578 regp = get_arm64_ftr_reg(sys_id); 1579 if (regp) { 1580 val &= ~regp->override->mask; 1581 val |= (regp->override->val & regp->override->mask); 1582 } 1583 1584 return val; 1585 } 1586 1587 #include <linux/irqchip/arm-gic-v3.h> 1588 1589 static bool 1590 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1591 { 1592 return true; 1593 } 1594 1595 static bool 1596 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1597 { 1598 int val, min, max; 1599 u64 tmp; 1600 1601 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1602 entry->field_width, 1603 entry->sign); 1604 1605 tmp = entry->min_field_value; 1606 tmp <<= entry->field_pos; 1607 1608 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1609 entry->field_width, 1610 entry->sign); 1611 1612 tmp = entry->max_field_value; 1613 tmp <<= entry->field_pos; 1614 1615 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1616 entry->field_width, 1617 entry->sign); 1618 1619 return val >= min && val <= max; 1620 } 1621 1622 static u64 1623 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1624 { 1625 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1626 if (scope == SCOPE_SYSTEM) 1627 return read_sanitised_ftr_reg(entry->sys_reg); 1628 else 1629 return __read_sysreg_by_encoding(entry->sys_reg); 1630 } 1631 1632 static bool 1633 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1634 { 1635 int mask; 1636 struct arm64_ftr_reg *regp; 1637 u64 val = read_scoped_sysreg(entry, scope); 1638 1639 regp = get_arm64_ftr_reg(entry->sys_reg); 1640 if (!regp) 1641 return false; 1642 1643 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1644 entry->field_pos, 1645 entry->field_width); 1646 if (!mask) 1647 return false; 1648 1649 return feature_matches(val, entry); 1650 } 1651 1652 static bool 1653 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1654 { 1655 u64 val = read_scoped_sysreg(entry, scope); 1656 return feature_matches(val, entry); 1657 } 1658 1659 const struct cpumask *system_32bit_el0_cpumask(void) 1660 { 1661 if (!system_supports_32bit_el0()) 1662 return cpu_none_mask; 1663 1664 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1665 return cpu_32bit_el0_mask; 1666 1667 return cpu_possible_mask; 1668 } 1669 1670 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1671 { 1672 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1673 } 1674 1675 static int __init parse_32bit_el0_param(char *str) 1676 { 1677 allow_mismatched_32bit_el0 = true; 1678 return 0; 1679 } 1680 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1681 1682 static ssize_t aarch32_el0_show(struct device *dev, 1683 struct device_attribute *attr, char *buf) 1684 { 1685 const struct cpumask *mask = system_32bit_el0_cpumask(); 1686 1687 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1688 } 1689 static const DEVICE_ATTR_RO(aarch32_el0); 1690 1691 static int __init aarch32_el0_sysfs_init(void) 1692 { 1693 struct device *dev_root; 1694 int ret = 0; 1695 1696 if (!allow_mismatched_32bit_el0) 1697 return 0; 1698 1699 dev_root = bus_get_dev_root(&cpu_subsys); 1700 if (dev_root) { 1701 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1702 put_device(dev_root); 1703 } 1704 return ret; 1705 } 1706 device_initcall(aarch32_el0_sysfs_init); 1707 1708 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1709 { 1710 if (!has_cpuid_feature(entry, scope)) 1711 return allow_mismatched_32bit_el0; 1712 1713 if (scope == SCOPE_SYSTEM) 1714 pr_info("detected: 32-bit EL0 Support\n"); 1715 1716 return true; 1717 } 1718 1719 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1720 { 1721 bool has_sre; 1722 1723 if (!has_cpuid_feature(entry, scope)) 1724 return false; 1725 1726 has_sre = gic_enable_sre(); 1727 if (!has_sre) 1728 pr_warn_once("%s present but disabled by higher exception level\n", 1729 entry->desc); 1730 1731 return has_sre; 1732 } 1733 1734 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1735 int scope) 1736 { 1737 u64 ctr; 1738 1739 if (scope == SCOPE_SYSTEM) 1740 ctr = arm64_ftr_reg_ctrel0.sys_val; 1741 else 1742 ctr = read_cpuid_effective_cachetype(); 1743 1744 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1745 } 1746 1747 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1748 { 1749 /* 1750 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1751 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1752 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1753 * value. 1754 */ 1755 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1756 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1757 } 1758 1759 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1760 int scope) 1761 { 1762 u64 ctr; 1763 1764 if (scope == SCOPE_SYSTEM) 1765 ctr = arm64_ftr_reg_ctrel0.sys_val; 1766 else 1767 ctr = read_cpuid_cachetype(); 1768 1769 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1770 } 1771 1772 static bool __maybe_unused 1773 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1774 { 1775 /* 1776 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1777 * may share TLB entries with a CPU stuck in the crashed 1778 * kernel. 1779 */ 1780 if (is_kdump_kernel()) 1781 return false; 1782 1783 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1784 return false; 1785 1786 return has_cpuid_feature(entry, scope); 1787 } 1788 1789 static bool __meltdown_safe = true; 1790 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1791 1792 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1793 int scope) 1794 { 1795 /* List of CPUs that are not vulnerable and don't need KPTI */ 1796 static const struct midr_range kpti_safe_list[] = { 1797 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1798 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1799 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1800 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1801 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1802 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1803 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1804 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1805 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1806 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1807 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1808 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1809 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1810 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1811 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1812 { /* sentinel */ } 1813 }; 1814 char const *str = "kpti command line option"; 1815 bool meltdown_safe; 1816 1817 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1818 1819 /* Defer to CPU feature registers */ 1820 if (has_cpuid_feature(entry, scope)) 1821 meltdown_safe = true; 1822 1823 if (!meltdown_safe) 1824 __meltdown_safe = false; 1825 1826 /* 1827 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1828 * ThunderX leads to apparent I-cache corruption of kernel text, which 1829 * ends as well as you might imagine. Don't even try. We cannot rely 1830 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1831 * because cpucap detection order may change. However, since we know 1832 * affected CPUs are always in a homogeneous configuration, it is 1833 * safe to rely on this_cpu_has_cap() here. 1834 */ 1835 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1836 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1837 __kpti_forced = -1; 1838 } 1839 1840 /* Useful for KASLR robustness */ 1841 if (kaslr_enabled() && kaslr_requires_kpti()) { 1842 if (!__kpti_forced) { 1843 str = "KASLR"; 1844 __kpti_forced = 1; 1845 } 1846 } 1847 1848 if (cpu_mitigations_off() && !__kpti_forced) { 1849 str = "mitigations=off"; 1850 __kpti_forced = -1; 1851 } 1852 1853 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1854 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1855 return false; 1856 } 1857 1858 /* Forced? */ 1859 if (__kpti_forced) { 1860 pr_info_once("kernel page table isolation forced %s by %s\n", 1861 __kpti_forced > 0 ? "ON" : "OFF", str); 1862 return __kpti_forced > 0; 1863 } 1864 1865 return !meltdown_safe; 1866 } 1867 1868 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1869 { 1870 /* 1871 * Although the Apple M2 family appears to support NV1, the 1872 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1873 * that it doesn't support NV1 at all. 1874 */ 1875 static const struct midr_range nv1_ni_list[] = { 1876 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1877 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1878 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1879 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1880 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1881 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1882 {} 1883 }; 1884 1885 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1886 !(has_cpuid_feature(entry, scope) || 1887 is_midr_in_range_list(nv1_ni_list))); 1888 } 1889 1890 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1891 static bool has_lpa2_at_stage1(u64 mmfr0) 1892 { 1893 unsigned int tgran; 1894 1895 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1896 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1897 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1898 } 1899 1900 static bool has_lpa2_at_stage2(u64 mmfr0) 1901 { 1902 unsigned int tgran; 1903 1904 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1905 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1906 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1907 } 1908 1909 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1910 { 1911 u64 mmfr0; 1912 1913 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1914 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1915 } 1916 #else 1917 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1918 { 1919 return false; 1920 } 1921 #endif 1922 1923 #ifdef CONFIG_HW_PERF_EVENTS 1924 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1925 { 1926 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1927 unsigned int pmuver; 1928 1929 /* 1930 * PMUVer follows the standard ID scheme for an unsigned field with the 1931 * exception of 0xF (IMP_DEF) which is treated specially and implies 1932 * FEAT_PMUv3 is not implemented. 1933 * 1934 * See DDI0487L.a D24.1.3.2 for more details. 1935 */ 1936 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1937 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1938 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1939 return false; 1940 1941 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1942 } 1943 #endif 1944 1945 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1946 { 1947 if (__this_cpu_read(this_cpu_vector) == vectors) { 1948 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1949 1950 __this_cpu_write(this_cpu_vector, v); 1951 } 1952 1953 } 1954 1955 static int __init parse_kpti(char *str) 1956 { 1957 bool enabled; 1958 int ret = kstrtobool(str, &enabled); 1959 1960 if (ret) 1961 return ret; 1962 1963 __kpti_forced = enabled ? 1 : -1; 1964 return 0; 1965 } 1966 early_param("kpti", parse_kpti); 1967 1968 #ifdef CONFIG_ARM64_HW_AFDBM 1969 static struct cpumask dbm_cpus __read_mostly; 1970 1971 static inline void __cpu_enable_hw_dbm(void) 1972 { 1973 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1974 1975 write_sysreg(tcr, tcr_el1); 1976 isb(); 1977 local_flush_tlb_all(); 1978 } 1979 1980 static bool cpu_has_broken_dbm(void) 1981 { 1982 /* List of CPUs which have broken DBM support. */ 1983 static const struct midr_range cpus[] = { 1984 #ifdef CONFIG_ARM64_ERRATUM_1024718 1985 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1986 /* Kryo4xx Silver (rdpe => r1p0) */ 1987 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1988 #endif 1989 #ifdef CONFIG_ARM64_ERRATUM_2051678 1990 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1991 #endif 1992 {}, 1993 }; 1994 1995 return is_midr_in_range_list(cpus); 1996 } 1997 1998 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1999 { 2000 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2001 !cpu_has_broken_dbm(); 2002 } 2003 2004 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2005 { 2006 if (cpu_can_use_dbm(cap)) { 2007 __cpu_enable_hw_dbm(); 2008 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2009 } 2010 } 2011 2012 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2013 int __unused) 2014 { 2015 /* 2016 * DBM is a non-conflicting feature. i.e, the kernel can safely 2017 * run a mix of CPUs with and without the feature. So, we 2018 * unconditionally enable the capability to allow any late CPU 2019 * to use the feature. We only enable the control bits on the 2020 * CPU, if it is supported. 2021 */ 2022 2023 return true; 2024 } 2025 2026 #endif 2027 2028 #ifdef CONFIG_ARM64_AMU_EXTN 2029 2030 /* 2031 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2032 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2033 * information regarding all the events that it supports. When a CPU bit is 2034 * set in the cpumask, the user of this feature can only rely on the presence 2035 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2036 * counters are enabled or access to these counters is enabled by code 2037 * executed at higher exception levels (firmware). 2038 */ 2039 static struct cpumask amu_cpus __read_mostly; 2040 2041 bool cpu_has_amu_feat(int cpu) 2042 { 2043 return cpumask_test_cpu(cpu, &amu_cpus); 2044 } 2045 2046 int get_cpu_with_amu_feat(void) 2047 { 2048 return cpumask_any(&amu_cpus); 2049 } 2050 2051 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2052 { 2053 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2054 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2055 2056 /* 0 reference values signal broken/disabled counters */ 2057 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2058 update_freq_counters_refs(); 2059 } 2060 } 2061 2062 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2063 int __unused) 2064 { 2065 /* 2066 * The AMU extension is a non-conflicting feature: the kernel can 2067 * safely run a mix of CPUs with and without support for the 2068 * activity monitors extension. Therefore, unconditionally enable 2069 * the capability to allow any late CPU to use the feature. 2070 * 2071 * With this feature unconditionally enabled, the cpu_enable 2072 * function will be called for all CPUs that match the criteria, 2073 * including secondary and hotplugged, marking this feature as 2074 * present on that respective CPU. The enable function will also 2075 * print a detection message. 2076 */ 2077 2078 return true; 2079 } 2080 #else 2081 int get_cpu_with_amu_feat(void) 2082 { 2083 return nr_cpu_ids; 2084 } 2085 #endif 2086 2087 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2088 { 2089 return is_kernel_in_hyp_mode(); 2090 } 2091 2092 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2093 { 2094 /* 2095 * Copy register values that aren't redirected by hardware. 2096 * 2097 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2098 * this value to tpidr_el2 before we patch the code. Once we've done 2099 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2100 * do anything here. 2101 */ 2102 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2103 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2104 } 2105 2106 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2107 int scope) 2108 { 2109 if (kvm_get_mode() != KVM_MODE_NV) 2110 return false; 2111 2112 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2113 pr_warn("unavailable: %s\n", cap->desc); 2114 return false; 2115 } 2116 2117 return true; 2118 } 2119 2120 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2121 int __unused) 2122 { 2123 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2124 } 2125 2126 bool cpu_supports_bbml2_noabort(void) 2127 { 2128 /* 2129 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2130 * as possible. This list is therefore an allow-list of known-good 2131 * implementations that both support BBML2 and additionally, fulfill the 2132 * extra constraint of never generating TLB conflict aborts when using 2133 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2134 * kernel contexts difficult to prove safe against recursive aborts). 2135 * 2136 * Note that implementations can only be considered "known-good" if their 2137 * implementors attest to the fact that the implementation never raises 2138 * TLB conflict aborts for BBML2 mapping granularity changes. 2139 */ 2140 static const struct midr_range supports_bbml2_noabort_list[] = { 2141 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2142 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2143 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2144 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2145 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2146 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2147 {} 2148 }; 2149 2150 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2151 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2152 return false; 2153 2154 /* 2155 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2156 * about whether the MIDR check passes. 2157 */ 2158 2159 return true; 2160 } 2161 2162 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2163 { 2164 return cpu_supports_bbml2_noabort(); 2165 } 2166 2167 #ifdef CONFIG_ARM64_PAN 2168 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2169 { 2170 /* 2171 * We modify PSTATE. This won't work from irq context as the PSTATE 2172 * is discarded once we return from the exception. 2173 */ 2174 WARN_ON_ONCE(in_interrupt()); 2175 2176 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2177 set_pstate_pan(1); 2178 } 2179 #endif /* CONFIG_ARM64_PAN */ 2180 2181 #ifdef CONFIG_ARM64_RAS_EXTN 2182 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2183 { 2184 /* Firmware may have left a deferred SError in this register. */ 2185 write_sysreg_s(0, SYS_DISR_EL1); 2186 } 2187 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2188 { 2189 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2190 { 2191 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2192 }, 2193 { 2194 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2195 }, 2196 { 2197 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2198 }, 2199 }; 2200 2201 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2202 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2203 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2204 } 2205 #endif /* CONFIG_ARM64_RAS_EXTN */ 2206 2207 #ifdef CONFIG_ARM64_PTR_AUTH 2208 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2209 { 2210 int boot_val, sec_val; 2211 2212 /* We don't expect to be called with SCOPE_SYSTEM */ 2213 WARN_ON(scope == SCOPE_SYSTEM); 2214 /* 2215 * The ptr-auth feature levels are not intercompatible with lower 2216 * levels. Hence we must match ptr-auth feature level of the secondary 2217 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2218 * from the sanitised register whereas direct register read is done for 2219 * the secondary CPUs. 2220 * The sanitised feature state is guaranteed to match that of the 2221 * boot CPU as a mismatched secondary CPU is parked before it gets 2222 * a chance to update the state, with the capability. 2223 */ 2224 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2225 entry->field_pos, entry->sign); 2226 if (scope & SCOPE_BOOT_CPU) 2227 return boot_val >= entry->min_field_value; 2228 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2229 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2230 entry->field_pos, entry->sign); 2231 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2232 } 2233 2234 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2235 int scope) 2236 { 2237 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2238 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2239 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2240 2241 return apa || apa3 || api; 2242 } 2243 2244 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2245 int __unused) 2246 { 2247 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2248 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2249 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2250 2251 return gpa || gpa3 || gpi; 2252 } 2253 #endif /* CONFIG_ARM64_PTR_AUTH */ 2254 2255 #ifdef CONFIG_ARM64_E0PD 2256 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2257 { 2258 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2259 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2260 } 2261 #endif /* CONFIG_ARM64_E0PD */ 2262 2263 #ifdef CONFIG_ARM64_PSEUDO_NMI 2264 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2265 int scope) 2266 { 2267 /* 2268 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2269 * feature, so will be detected earlier. 2270 */ 2271 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2272 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2273 return false; 2274 2275 return enable_pseudo_nmi; 2276 } 2277 2278 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2279 int scope) 2280 { 2281 /* 2282 * If we're not using priority masking then we won't be poking PMR_EL1, 2283 * and there's no need to relax synchronization of writes to it, and 2284 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2285 * that. 2286 * 2287 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2288 * feature, so will be detected earlier. 2289 */ 2290 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2291 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2292 return false; 2293 2294 /* 2295 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2296 * hint for interrupt distribution, a DSB is not necessary when 2297 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2298 * 2299 * Linux itself doesn't use 1:N distribution, so has no need to 2300 * set PMHE. The only reason to have it set is if EL3 requires it 2301 * (and we can't change it). 2302 */ 2303 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2304 } 2305 #endif 2306 2307 #ifdef CONFIG_ARM64_BTI 2308 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2309 { 2310 /* 2311 * Use of X16/X17 for tail-calls and trampolines that jump to 2312 * function entry points using BR is a requirement for 2313 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2314 * So, be strict and forbid other BRs using other registers to 2315 * jump onto a PACIxSP instruction: 2316 */ 2317 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2318 isb(); 2319 } 2320 #endif /* CONFIG_ARM64_BTI */ 2321 2322 #ifdef CONFIG_ARM64_MTE 2323 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2324 { 2325 static bool cleared_zero_page = false; 2326 2327 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2328 2329 mte_cpu_setup(); 2330 2331 /* 2332 * Clear the tags in the zero page. This needs to be done via the 2333 * linear map which has the Tagged attribute. Since this page is 2334 * always mapped as pte_special(), set_pte_at() will not attempt to 2335 * clear the tags or set PG_mte_tagged. 2336 */ 2337 if (!cleared_zero_page) { 2338 cleared_zero_page = true; 2339 mte_clear_page_tags(lm_alias(empty_zero_page)); 2340 } 2341 2342 kasan_init_hw_tags_cpu(); 2343 } 2344 #endif /* CONFIG_ARM64_MTE */ 2345 2346 static void user_feature_fixup(void) 2347 { 2348 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2349 struct arm64_ftr_reg *regp; 2350 2351 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2352 if (regp) 2353 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2354 } 2355 2356 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2357 struct arm64_ftr_reg *regp; 2358 2359 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2360 if (regp) 2361 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2362 } 2363 } 2364 2365 static void elf_hwcap_fixup(void) 2366 { 2367 #ifdef CONFIG_COMPAT 2368 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2369 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2370 #endif /* CONFIG_COMPAT */ 2371 } 2372 2373 #ifdef CONFIG_KVM 2374 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2375 { 2376 return kvm_get_mode() == KVM_MODE_PROTECTED; 2377 } 2378 #endif /* CONFIG_KVM */ 2379 2380 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2381 { 2382 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2383 } 2384 2385 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2386 { 2387 set_pstate_dit(1); 2388 } 2389 2390 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2391 { 2392 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2393 } 2394 2395 #ifdef CONFIG_ARM64_POE 2396 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2397 { 2398 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2399 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2400 } 2401 #endif 2402 2403 #ifdef CONFIG_ARM64_GCS 2404 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2405 { 2406 /* GCSPR_EL0 is always readable */ 2407 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2408 } 2409 #endif 2410 2411 /* Internal helper functions to match cpu capability type */ 2412 static bool 2413 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2414 { 2415 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2416 } 2417 2418 static bool 2419 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2420 { 2421 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2422 } 2423 2424 static bool 2425 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2426 { 2427 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2428 } 2429 2430 static bool 2431 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2432 { 2433 if (!has_cpuid_feature(entry, scope)) 2434 return false; 2435 2436 /* Check firmware actually enabled MPAM on this cpu. */ 2437 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2438 } 2439 2440 static void 2441 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2442 { 2443 /* 2444 * Access by the kernel (at EL1) should use the reserved PARTID 2445 * which is configured unrestricted. This avoids priority-inversion 2446 * where latency sensitive tasks have to wait for a task that has 2447 * been throttled to release the lock. 2448 */ 2449 write_sysreg_s(0, SYS_MPAM1_EL1); 2450 } 2451 2452 static bool 2453 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2454 { 2455 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2456 2457 return idr & MPAMIDR_EL1_HAS_HCR; 2458 } 2459 2460 static bool 2461 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2462 { 2463 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2464 return false; 2465 2466 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2467 } 2468 2469 static const struct arm64_cpu_capabilities arm64_features[] = { 2470 { 2471 .capability = ARM64_ALWAYS_BOOT, 2472 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2473 .matches = has_always, 2474 }, 2475 { 2476 .capability = ARM64_ALWAYS_SYSTEM, 2477 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2478 .matches = has_always, 2479 }, 2480 { 2481 .desc = "GICv3 CPU interface", 2482 .capability = ARM64_HAS_GICV3_CPUIF, 2483 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2484 .matches = has_useable_gicv3_cpuif, 2485 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2486 }, 2487 { 2488 .desc = "Enhanced Counter Virtualization", 2489 .capability = ARM64_HAS_ECV, 2490 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2491 .matches = has_cpuid_feature, 2492 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2493 }, 2494 { 2495 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2496 .capability = ARM64_HAS_ECV_CNTPOFF, 2497 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2498 .matches = has_cpuid_feature, 2499 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2500 }, 2501 #ifdef CONFIG_ARM64_PAN 2502 { 2503 .desc = "Privileged Access Never", 2504 .capability = ARM64_HAS_PAN, 2505 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2506 .matches = has_cpuid_feature, 2507 .cpu_enable = cpu_enable_pan, 2508 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2509 }, 2510 #endif /* CONFIG_ARM64_PAN */ 2511 #ifdef CONFIG_ARM64_EPAN 2512 { 2513 .desc = "Enhanced Privileged Access Never", 2514 .capability = ARM64_HAS_EPAN, 2515 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2516 .matches = has_cpuid_feature, 2517 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2518 }, 2519 #endif /* CONFIG_ARM64_EPAN */ 2520 #ifdef CONFIG_ARM64_LSE_ATOMICS 2521 { 2522 .desc = "LSE atomic instructions", 2523 .capability = ARM64_HAS_LSE_ATOMICS, 2524 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2525 .matches = has_cpuid_feature, 2526 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2527 }, 2528 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2529 { 2530 .desc = "Virtualization Host Extensions", 2531 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2532 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2533 .matches = runs_at_el2, 2534 .cpu_enable = cpu_copy_el2regs, 2535 }, 2536 { 2537 .desc = "Nested Virtualization Support", 2538 .capability = ARM64_HAS_NESTED_VIRT, 2539 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2540 .matches = has_nested_virt_support, 2541 .match_list = (const struct arm64_cpu_capabilities []){ 2542 { 2543 .matches = has_cpuid_feature, 2544 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2545 }, 2546 { 2547 .matches = has_cpuid_feature, 2548 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2549 }, 2550 { /* Sentinel */ } 2551 }, 2552 }, 2553 { 2554 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2555 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2556 .matches = has_32bit_el0, 2557 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2558 }, 2559 #ifdef CONFIG_KVM 2560 { 2561 .desc = "32-bit EL1 Support", 2562 .capability = ARM64_HAS_32BIT_EL1, 2563 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2564 .matches = has_cpuid_feature, 2565 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2566 }, 2567 { 2568 .desc = "Protected KVM", 2569 .capability = ARM64_KVM_PROTECTED_MODE, 2570 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2571 .matches = is_kvm_protected_mode, 2572 }, 2573 { 2574 .desc = "HCRX_EL2 register", 2575 .capability = ARM64_HAS_HCX, 2576 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2577 .matches = has_cpuid_feature, 2578 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2579 }, 2580 #endif 2581 { 2582 .desc = "Kernel page table isolation (KPTI)", 2583 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2584 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2585 .cpu_enable = cpu_enable_kpti, 2586 .matches = unmap_kernel_at_el0, 2587 /* 2588 * The ID feature fields below are used to indicate that 2589 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2590 * more details. 2591 */ 2592 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2593 }, 2594 { 2595 .capability = ARM64_HAS_FPSIMD, 2596 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2597 .matches = has_cpuid_feature, 2598 .cpu_enable = cpu_enable_fpsimd, 2599 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2600 }, 2601 #ifdef CONFIG_ARM64_PMEM 2602 { 2603 .desc = "Data cache clean to Point of Persistence", 2604 .capability = ARM64_HAS_DCPOP, 2605 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2606 .matches = has_cpuid_feature, 2607 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2608 }, 2609 { 2610 .desc = "Data cache clean to Point of Deep Persistence", 2611 .capability = ARM64_HAS_DCPODP, 2612 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2613 .matches = has_cpuid_feature, 2614 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2615 }, 2616 #endif 2617 #ifdef CONFIG_ARM64_SVE 2618 { 2619 .desc = "Scalable Vector Extension", 2620 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2621 .capability = ARM64_SVE, 2622 .cpu_enable = cpu_enable_sve, 2623 .matches = has_cpuid_feature, 2624 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2625 }, 2626 #endif /* CONFIG_ARM64_SVE */ 2627 #ifdef CONFIG_ARM64_RAS_EXTN 2628 { 2629 .desc = "RAS Extension Support", 2630 .capability = ARM64_HAS_RAS_EXTN, 2631 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2632 .matches = has_cpuid_feature, 2633 .cpu_enable = cpu_clear_disr, 2634 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2635 }, 2636 { 2637 .desc = "RASv1p1 Extension Support", 2638 .capability = ARM64_HAS_RASV1P1_EXTN, 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .matches = has_rasv1p1, 2641 }, 2642 #endif /* CONFIG_ARM64_RAS_EXTN */ 2643 #ifdef CONFIG_ARM64_AMU_EXTN 2644 { 2645 .desc = "Activity Monitors Unit (AMU)", 2646 .capability = ARM64_HAS_AMU_EXTN, 2647 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2648 .matches = has_amu, 2649 .cpu_enable = cpu_amu_enable, 2650 .cpus = &amu_cpus, 2651 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2652 }, 2653 #endif /* CONFIG_ARM64_AMU_EXTN */ 2654 { 2655 .desc = "Data cache clean to the PoU not required for I/D coherence", 2656 .capability = ARM64_HAS_CACHE_IDC, 2657 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2658 .matches = has_cache_idc, 2659 .cpu_enable = cpu_emulate_effective_ctr, 2660 }, 2661 { 2662 .desc = "Instruction cache invalidation not required for I/D coherence", 2663 .capability = ARM64_HAS_CACHE_DIC, 2664 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2665 .matches = has_cache_dic, 2666 }, 2667 { 2668 .desc = "Stage-2 Force Write-Back", 2669 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2670 .capability = ARM64_HAS_STAGE2_FWB, 2671 .matches = has_cpuid_feature, 2672 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2673 }, 2674 { 2675 .desc = "ARMv8.4 Translation Table Level", 2676 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2677 .capability = ARM64_HAS_ARMv8_4_TTL, 2678 .matches = has_cpuid_feature, 2679 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2680 }, 2681 { 2682 .desc = "TLB range maintenance instructions", 2683 .capability = ARM64_HAS_TLB_RANGE, 2684 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2685 .matches = has_cpuid_feature, 2686 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2687 }, 2688 #ifdef CONFIG_ARM64_HW_AFDBM 2689 { 2690 .desc = "Hardware dirty bit management", 2691 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2692 .capability = ARM64_HW_DBM, 2693 .matches = has_hw_dbm, 2694 .cpu_enable = cpu_enable_hw_dbm, 2695 .cpus = &dbm_cpus, 2696 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2697 }, 2698 #endif 2699 #ifdef CONFIG_ARM64_HAFT 2700 { 2701 .desc = "Hardware managed Access Flag for Table Descriptors", 2702 /* 2703 * Contrary to the page/block access flag, the table access flag 2704 * cannot be emulated in software (no access fault will occur). 2705 * Therefore this should be used only if it's supported system 2706 * wide. 2707 */ 2708 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2709 .capability = ARM64_HAFT, 2710 .matches = has_cpuid_feature, 2711 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2712 }, 2713 #endif 2714 { 2715 .desc = "CRC32 instructions", 2716 .capability = ARM64_HAS_CRC32, 2717 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2718 .matches = has_cpuid_feature, 2719 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2720 }, 2721 { 2722 .desc = "Speculative Store Bypassing Safe (SSBS)", 2723 .capability = ARM64_SSBS, 2724 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2725 .matches = has_cpuid_feature, 2726 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2727 }, 2728 #ifdef CONFIG_ARM64_CNP 2729 { 2730 .desc = "Common not Private translations", 2731 .capability = ARM64_HAS_CNP, 2732 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2733 .matches = has_useable_cnp, 2734 .cpu_enable = cpu_enable_cnp, 2735 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2736 }, 2737 #endif 2738 { 2739 .desc = "Speculation barrier (SB)", 2740 .capability = ARM64_HAS_SB, 2741 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2742 .matches = has_cpuid_feature, 2743 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2744 }, 2745 #ifdef CONFIG_ARM64_PTR_AUTH 2746 { 2747 .desc = "Address authentication (architected QARMA5 algorithm)", 2748 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2749 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2750 .matches = has_address_auth_cpucap, 2751 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2752 }, 2753 { 2754 .desc = "Address authentication (architected QARMA3 algorithm)", 2755 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2756 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2757 .matches = has_address_auth_cpucap, 2758 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2759 }, 2760 { 2761 .desc = "Address authentication (IMP DEF algorithm)", 2762 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2763 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2764 .matches = has_address_auth_cpucap, 2765 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2766 }, 2767 { 2768 .capability = ARM64_HAS_ADDRESS_AUTH, 2769 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2770 .matches = has_address_auth_metacap, 2771 }, 2772 { 2773 .desc = "Generic authentication (architected QARMA5 algorithm)", 2774 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2775 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2776 .matches = has_cpuid_feature, 2777 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2778 }, 2779 { 2780 .desc = "Generic authentication (architected QARMA3 algorithm)", 2781 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2782 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2783 .matches = has_cpuid_feature, 2784 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2785 }, 2786 { 2787 .desc = "Generic authentication (IMP DEF algorithm)", 2788 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2789 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2790 .matches = has_cpuid_feature, 2791 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2792 }, 2793 { 2794 .capability = ARM64_HAS_GENERIC_AUTH, 2795 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2796 .matches = has_generic_auth, 2797 }, 2798 #endif /* CONFIG_ARM64_PTR_AUTH */ 2799 #ifdef CONFIG_ARM64_PSEUDO_NMI 2800 { 2801 /* 2802 * Depends on having GICv3 2803 */ 2804 .desc = "IRQ priority masking", 2805 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2806 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2807 .matches = can_use_gic_priorities, 2808 }, 2809 { 2810 /* 2811 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2812 */ 2813 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2814 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2815 .matches = has_gic_prio_relaxed_sync, 2816 }, 2817 #endif 2818 #ifdef CONFIG_ARM64_E0PD 2819 { 2820 .desc = "E0PD", 2821 .capability = ARM64_HAS_E0PD, 2822 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2823 .cpu_enable = cpu_enable_e0pd, 2824 .matches = has_cpuid_feature, 2825 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2826 }, 2827 #endif 2828 { 2829 .desc = "Random Number Generator", 2830 .capability = ARM64_HAS_RNG, 2831 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2832 .matches = has_cpuid_feature, 2833 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2834 }, 2835 #ifdef CONFIG_ARM64_BTI 2836 { 2837 .desc = "Branch Target Identification", 2838 .capability = ARM64_BTI, 2839 #ifdef CONFIG_ARM64_BTI_KERNEL 2840 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2841 #else 2842 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2843 #endif 2844 .matches = has_cpuid_feature, 2845 .cpu_enable = bti_enable, 2846 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2847 }, 2848 #endif 2849 #ifdef CONFIG_ARM64_MTE 2850 { 2851 .desc = "Memory Tagging Extension", 2852 .capability = ARM64_MTE, 2853 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2854 .matches = has_cpuid_feature, 2855 .cpu_enable = cpu_enable_mte, 2856 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2857 }, 2858 { 2859 .desc = "Asymmetric MTE Tag Check Fault", 2860 .capability = ARM64_MTE_ASYMM, 2861 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2862 .matches = has_cpuid_feature, 2863 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2864 }, 2865 { 2866 .desc = "FAR on MTE Tag Check Fault", 2867 .capability = ARM64_MTE_FAR, 2868 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2869 .matches = has_cpuid_feature, 2870 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2871 }, 2872 { 2873 .desc = "Store Only MTE Tag Check", 2874 .capability = ARM64_MTE_STORE_ONLY, 2875 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2876 .matches = has_cpuid_feature, 2877 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2878 }, 2879 #endif /* CONFIG_ARM64_MTE */ 2880 { 2881 .desc = "RCpc load-acquire (LDAPR)", 2882 .capability = ARM64_HAS_LDAPR, 2883 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2884 .matches = has_cpuid_feature, 2885 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2886 }, 2887 { 2888 .desc = "Fine Grained Traps", 2889 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2890 .capability = ARM64_HAS_FGT, 2891 .matches = has_cpuid_feature, 2892 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2893 }, 2894 { 2895 .desc = "Fine Grained Traps 2", 2896 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2897 .capability = ARM64_HAS_FGT2, 2898 .matches = has_cpuid_feature, 2899 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2900 }, 2901 #ifdef CONFIG_ARM64_SME 2902 { 2903 .desc = "Scalable Matrix Extension", 2904 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2905 .capability = ARM64_SME, 2906 .matches = has_cpuid_feature, 2907 .cpu_enable = cpu_enable_sme, 2908 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2909 }, 2910 /* FA64 should be sorted after the base SME capability */ 2911 { 2912 .desc = "FA64", 2913 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2914 .capability = ARM64_SME_FA64, 2915 .matches = has_cpuid_feature, 2916 .cpu_enable = cpu_enable_fa64, 2917 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2918 }, 2919 { 2920 .desc = "SME2", 2921 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2922 .capability = ARM64_SME2, 2923 .matches = has_cpuid_feature, 2924 .cpu_enable = cpu_enable_sme2, 2925 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2926 }, 2927 #endif /* CONFIG_ARM64_SME */ 2928 { 2929 .desc = "WFx with timeout", 2930 .capability = ARM64_HAS_WFXT, 2931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2932 .matches = has_cpuid_feature, 2933 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2934 }, 2935 { 2936 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2937 .capability = ARM64_HAS_TIDCP1, 2938 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2939 .matches = has_cpuid_feature, 2940 .cpu_enable = cpu_trap_el0_impdef, 2941 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2942 }, 2943 { 2944 .desc = "Data independent timing control (DIT)", 2945 .capability = ARM64_HAS_DIT, 2946 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2947 .matches = has_cpuid_feature, 2948 .cpu_enable = cpu_enable_dit, 2949 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2950 }, 2951 { 2952 .desc = "Memory Copy and Memory Set instructions", 2953 .capability = ARM64_HAS_MOPS, 2954 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2955 .matches = has_cpuid_feature, 2956 .cpu_enable = cpu_enable_mops, 2957 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2958 }, 2959 { 2960 .capability = ARM64_HAS_TCR2, 2961 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2962 .matches = has_cpuid_feature, 2963 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2964 }, 2965 { 2966 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2967 .capability = ARM64_HAS_S1PIE, 2968 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2969 .matches = has_cpuid_feature, 2970 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2971 }, 2972 { 2973 .desc = "VHE for hypervisor only", 2974 .capability = ARM64_KVM_HVHE, 2975 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2976 .matches = hvhe_possible, 2977 }, 2978 { 2979 .desc = "Enhanced Virtualization Traps", 2980 .capability = ARM64_HAS_EVT, 2981 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2982 .matches = has_cpuid_feature, 2983 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2984 }, 2985 { 2986 .desc = "BBM Level 2 without TLB conflict abort", 2987 .capability = ARM64_HAS_BBML2_NOABORT, 2988 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2989 .matches = has_bbml2_noabort, 2990 }, 2991 { 2992 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2993 .capability = ARM64_HAS_LPA2, 2994 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2995 .matches = has_lpa2, 2996 }, 2997 { 2998 .desc = "FPMR", 2999 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3000 .capability = ARM64_HAS_FPMR, 3001 .matches = has_cpuid_feature, 3002 .cpu_enable = cpu_enable_fpmr, 3003 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3004 }, 3005 #ifdef CONFIG_ARM64_VA_BITS_52 3006 { 3007 .capability = ARM64_HAS_VA52, 3008 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3009 .matches = has_cpuid_feature, 3010 #ifdef CONFIG_ARM64_64K_PAGES 3011 .desc = "52-bit Virtual Addressing (LVA)", 3012 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3013 #else 3014 .desc = "52-bit Virtual Addressing (LPA2)", 3015 #ifdef CONFIG_ARM64_4K_PAGES 3016 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3017 #else 3018 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3019 #endif 3020 #endif 3021 }, 3022 #endif 3023 { 3024 .desc = "Memory Partitioning And Monitoring", 3025 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3026 .capability = ARM64_MPAM, 3027 .matches = test_has_mpam, 3028 .cpu_enable = cpu_enable_mpam, 3029 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3030 }, 3031 { 3032 .desc = "Memory Partitioning And Monitoring Virtualisation", 3033 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3034 .capability = ARM64_MPAM_HCR, 3035 .matches = test_has_mpam_hcr, 3036 }, 3037 { 3038 .desc = "NV1", 3039 .capability = ARM64_HAS_HCR_NV1, 3040 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3041 .matches = has_nv1, 3042 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3043 }, 3044 #ifdef CONFIG_ARM64_POE 3045 { 3046 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3047 .capability = ARM64_HAS_S1POE, 3048 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3049 .matches = has_cpuid_feature, 3050 .cpu_enable = cpu_enable_poe, 3051 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3052 }, 3053 #endif 3054 #ifdef CONFIG_ARM64_GCS 3055 { 3056 .desc = "Guarded Control Stack (GCS)", 3057 .capability = ARM64_HAS_GCS, 3058 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3059 .cpu_enable = cpu_enable_gcs, 3060 .matches = has_cpuid_feature, 3061 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3062 }, 3063 #endif 3064 #ifdef CONFIG_HW_PERF_EVENTS 3065 { 3066 .desc = "PMUv3", 3067 .capability = ARM64_HAS_PMUV3, 3068 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3069 .matches = has_pmuv3, 3070 }, 3071 #endif 3072 { 3073 .desc = "SCTLR2", 3074 .capability = ARM64_HAS_SCTLR2, 3075 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3076 .matches = has_cpuid_feature, 3077 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3078 }, 3079 { 3080 .desc = "GICv5 CPU interface", 3081 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3082 .capability = ARM64_HAS_GICV5_CPUIF, 3083 .matches = has_cpuid_feature, 3084 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3085 }, 3086 { 3087 .desc = "GICv5 Legacy vCPU interface", 3088 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3089 .capability = ARM64_HAS_GICV5_LEGACY, 3090 .matches = test_has_gicv5_legacy, 3091 }, 3092 {}, 3093 }; 3094 3095 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3096 .matches = has_user_cpuid_feature, \ 3097 ARM64_CPUID_FIELDS(reg, field, min_value) 3098 3099 #define __HWCAP_CAP(name, cap_type, cap) \ 3100 .desc = name, \ 3101 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3102 .hwcap_type = cap_type, \ 3103 .hwcap = cap, \ 3104 3105 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3106 { \ 3107 __HWCAP_CAP(#cap, cap_type, cap) \ 3108 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3109 } 3110 3111 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3112 { \ 3113 __HWCAP_CAP(#cap, cap_type, cap) \ 3114 .matches = cpucap_multi_entry_cap_matches, \ 3115 .match_list = list, \ 3116 } 3117 3118 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3119 { \ 3120 __HWCAP_CAP(#cap, cap_type, cap) \ 3121 .matches = match, \ 3122 } 3123 3124 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3125 { \ 3126 __HWCAP_CAP(#cap, cap_type, cap) \ 3127 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3128 .matches = match, \ 3129 } 3130 3131 #ifdef CONFIG_ARM64_PTR_AUTH 3132 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3133 { 3134 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3135 }, 3136 { 3137 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3138 }, 3139 { 3140 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3141 }, 3142 {}, 3143 }; 3144 3145 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3146 { 3147 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3148 }, 3149 { 3150 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3151 }, 3152 { 3153 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3154 }, 3155 {}, 3156 }; 3157 #endif 3158 3159 #ifdef CONFIG_ARM64_SVE 3160 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3161 { 3162 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3163 } 3164 #endif 3165 3166 #ifdef CONFIG_ARM64_SME 3167 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3168 { 3169 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3170 } 3171 #endif 3172 3173 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3174 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3175 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3176 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3177 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3178 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3179 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3180 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3181 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3182 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3183 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3184 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3185 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3186 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3187 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3188 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3189 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3190 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3191 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3192 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3193 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3194 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3195 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3196 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3197 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3198 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3199 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3200 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3201 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3202 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3203 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3204 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3205 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3206 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3207 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3208 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3209 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3210 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3211 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3212 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3213 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3214 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3215 #ifdef CONFIG_ARM64_SVE 3216 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3217 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3218 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3219 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3220 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3221 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3222 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3223 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3224 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3225 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3226 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3227 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3228 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3229 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3230 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3231 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3232 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3233 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3234 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3235 #endif 3236 #ifdef CONFIG_ARM64_GCS 3237 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3238 #endif 3239 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3240 #ifdef CONFIG_ARM64_BTI 3241 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3242 #endif 3243 #ifdef CONFIG_ARM64_PTR_AUTH 3244 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3245 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3246 #endif 3247 #ifdef CONFIG_ARM64_MTE 3248 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3249 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3250 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3251 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3252 #endif /* CONFIG_ARM64_MTE */ 3253 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3254 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3255 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3256 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3257 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3258 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3259 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3260 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3261 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3262 #ifdef CONFIG_ARM64_SME 3263 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3264 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3265 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3266 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3267 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3268 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3269 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3270 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3271 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3272 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3273 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3274 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3275 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3276 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3277 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3278 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3279 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3280 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3281 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3282 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3283 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3284 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3285 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3286 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3287 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3288 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3289 #endif /* CONFIG_ARM64_SME */ 3290 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3291 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3292 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3293 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3294 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3295 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3296 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3297 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3298 #ifdef CONFIG_ARM64_POE 3299 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3300 #endif 3301 {}, 3302 }; 3303 3304 #ifdef CONFIG_COMPAT 3305 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3306 { 3307 /* 3308 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3309 * in line with that of arm32 as in vfp_init(). We make sure that the 3310 * check is future proof, by making sure value is non-zero. 3311 */ 3312 u32 mvfr1; 3313 3314 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3315 if (scope == SCOPE_SYSTEM) 3316 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3317 else 3318 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3319 3320 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3321 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3322 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3323 } 3324 #endif 3325 3326 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3327 #ifdef CONFIG_COMPAT 3328 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3329 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3330 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3331 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3332 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3333 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3334 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3335 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3336 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3337 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3338 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3339 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3340 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3341 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3342 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3343 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3344 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3345 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3346 #endif 3347 {}, 3348 }; 3349 3350 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3351 { 3352 switch (cap->hwcap_type) { 3353 case CAP_HWCAP: 3354 cpu_set_feature(cap->hwcap); 3355 break; 3356 #ifdef CONFIG_COMPAT 3357 case CAP_COMPAT_HWCAP: 3358 compat_elf_hwcap |= (u32)cap->hwcap; 3359 break; 3360 case CAP_COMPAT_HWCAP2: 3361 compat_elf_hwcap2 |= (u32)cap->hwcap; 3362 break; 3363 #endif 3364 default: 3365 WARN_ON(1); 3366 break; 3367 } 3368 } 3369 3370 /* Check if we have a particular HWCAP enabled */ 3371 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3372 { 3373 bool rc; 3374 3375 switch (cap->hwcap_type) { 3376 case CAP_HWCAP: 3377 rc = cpu_have_feature(cap->hwcap); 3378 break; 3379 #ifdef CONFIG_COMPAT 3380 case CAP_COMPAT_HWCAP: 3381 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3382 break; 3383 case CAP_COMPAT_HWCAP2: 3384 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3385 break; 3386 #endif 3387 default: 3388 WARN_ON(1); 3389 rc = false; 3390 } 3391 3392 return rc; 3393 } 3394 3395 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3396 { 3397 /* We support emulation of accesses to CPU ID feature registers */ 3398 cpu_set_named_feature(CPUID); 3399 for (; hwcaps->matches; hwcaps++) 3400 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3401 cap_set_elf_hwcap(hwcaps); 3402 } 3403 3404 static void update_cpu_capabilities(u16 scope_mask) 3405 { 3406 int i; 3407 const struct arm64_cpu_capabilities *caps; 3408 3409 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3410 for (i = 0; i < ARM64_NCAPS; i++) { 3411 bool match_all = false; 3412 bool caps_set = false; 3413 bool boot_cpu = false; 3414 3415 caps = cpucap_ptrs[i]; 3416 if (!caps || !(caps->type & scope_mask)) 3417 continue; 3418 3419 match_all = cpucap_match_all_early_cpus(caps); 3420 caps_set = cpus_have_cap(caps->capability); 3421 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3422 3423 /* 3424 * Unless it's a match-all CPUs feature, avoid probing if 3425 * already detected. 3426 */ 3427 if (!match_all && caps_set) 3428 continue; 3429 3430 /* 3431 * A match-all CPUs capability is only set when probing the 3432 * boot CPU. It may be cleared subsequently if not detected on 3433 * secondary ones. 3434 */ 3435 if (match_all && !caps_set && !boot_cpu) 3436 continue; 3437 3438 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3439 if (match_all) 3440 __clear_bit(caps->capability, system_cpucaps); 3441 continue; 3442 } 3443 3444 /* 3445 * Match-all CPUs capabilities are logged later when the 3446 * system capabilities are finalised. 3447 */ 3448 if (!match_all && caps->desc && !caps->cpus) 3449 pr_info("detected: %s\n", caps->desc); 3450 3451 __set_bit(caps->capability, system_cpucaps); 3452 3453 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3454 set_bit(caps->capability, boot_cpucaps); 3455 } 3456 } 3457 3458 /* 3459 * Enable all the available capabilities on this CPU. The capabilities 3460 * with BOOT_CPU scope are handled separately and hence skipped here. 3461 */ 3462 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3463 { 3464 int i; 3465 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3466 3467 for_each_available_cap(i) { 3468 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3469 3470 if (WARN_ON(!cap)) 3471 continue; 3472 3473 if (!(cap->type & non_boot_scope)) 3474 continue; 3475 3476 if (cap->cpu_enable) 3477 cap->cpu_enable(cap); 3478 } 3479 return 0; 3480 } 3481 3482 /* 3483 * Run through the enabled capabilities and enable() it on all active 3484 * CPUs 3485 */ 3486 static void __init enable_cpu_capabilities(u16 scope_mask) 3487 { 3488 int i; 3489 const struct arm64_cpu_capabilities *caps; 3490 bool boot_scope; 3491 3492 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3493 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3494 3495 for (i = 0; i < ARM64_NCAPS; i++) { 3496 caps = cpucap_ptrs[i]; 3497 if (!caps || !(caps->type & scope_mask) || 3498 !cpus_have_cap(caps->capability)) 3499 continue; 3500 3501 if (boot_scope && caps->cpu_enable) 3502 /* 3503 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3504 * before any secondary CPU boots. Thus, each secondary 3505 * will enable the capability as appropriate via 3506 * check_local_cpu_capabilities(). The only exception is 3507 * the boot CPU, for which the capability must be 3508 * enabled here. This approach avoids costly 3509 * stop_machine() calls for this case. 3510 */ 3511 caps->cpu_enable(caps); 3512 } 3513 3514 /* 3515 * For all non-boot scope capabilities, use stop_machine() 3516 * as it schedules the work allowing us to modify PSTATE, 3517 * instead of on_each_cpu() which uses an IPI, giving us a 3518 * PSTATE that disappears when we return. 3519 */ 3520 if (!boot_scope) 3521 stop_machine(cpu_enable_non_boot_scope_capabilities, 3522 NULL, cpu_online_mask); 3523 } 3524 3525 /* 3526 * Run through the list of capabilities to check for conflicts. 3527 * If the system has already detected a capability, take necessary 3528 * action on this CPU. 3529 */ 3530 static void verify_local_cpu_caps(u16 scope_mask) 3531 { 3532 int i; 3533 bool cpu_has_cap, system_has_cap; 3534 const struct arm64_cpu_capabilities *caps; 3535 3536 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3537 3538 for (i = 0; i < ARM64_NCAPS; i++) { 3539 caps = cpucap_ptrs[i]; 3540 if (!caps || !(caps->type & scope_mask)) 3541 continue; 3542 3543 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3544 system_has_cap = cpus_have_cap(caps->capability); 3545 3546 if (system_has_cap) { 3547 /* 3548 * Check if the new CPU misses an advertised feature, 3549 * which is not safe to miss. 3550 */ 3551 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3552 break; 3553 /* 3554 * We have to issue cpu_enable() irrespective of 3555 * whether the CPU has it or not, as it is enabeld 3556 * system wide. It is upto the call back to take 3557 * appropriate action on this CPU. 3558 */ 3559 if (caps->cpu_enable) 3560 caps->cpu_enable(caps); 3561 } else { 3562 /* 3563 * Check if the CPU has this capability if it isn't 3564 * safe to have when the system doesn't. 3565 */ 3566 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3567 break; 3568 } 3569 } 3570 3571 if (i < ARM64_NCAPS) { 3572 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3573 smp_processor_id(), caps->capability, 3574 caps->desc, system_has_cap, cpu_has_cap); 3575 3576 if (cpucap_panic_on_conflict(caps)) 3577 cpu_panic_kernel(); 3578 else 3579 cpu_die_early(); 3580 } 3581 } 3582 3583 /* 3584 * Check for CPU features that are used in early boot 3585 * based on the Boot CPU value. 3586 */ 3587 static void check_early_cpu_features(void) 3588 { 3589 verify_cpu_asid_bits(); 3590 3591 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3592 } 3593 3594 static void 3595 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3596 { 3597 3598 for (; caps->matches; caps++) 3599 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3600 pr_crit("CPU%d: missing HWCAP: %s\n", 3601 smp_processor_id(), caps->desc); 3602 cpu_die_early(); 3603 } 3604 } 3605 3606 static void verify_local_elf_hwcaps(void) 3607 { 3608 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3609 3610 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3611 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3612 } 3613 3614 static void verify_sve_features(void) 3615 { 3616 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3617 3618 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3619 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3620 smp_processor_id()); 3621 cpu_die_early(); 3622 } 3623 3624 cpacr_restore(cpacr); 3625 } 3626 3627 static void verify_sme_features(void) 3628 { 3629 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3630 3631 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3632 pr_crit("CPU%d: SME: vector length support mismatch\n", 3633 smp_processor_id()); 3634 cpu_die_early(); 3635 } 3636 3637 cpacr_restore(cpacr); 3638 } 3639 3640 static void verify_hyp_capabilities(void) 3641 { 3642 u64 safe_mmfr1, mmfr0, mmfr1; 3643 int parange, ipa_max; 3644 unsigned int safe_vmid_bits, vmid_bits; 3645 3646 if (!IS_ENABLED(CONFIG_KVM)) 3647 return; 3648 3649 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3650 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3651 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3652 3653 /* Verify VMID bits */ 3654 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3655 vmid_bits = get_vmid_bits(mmfr1); 3656 if (vmid_bits < safe_vmid_bits) { 3657 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3658 cpu_die_early(); 3659 } 3660 3661 /* Verify IPA range */ 3662 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3663 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3664 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3665 if (ipa_max < get_kvm_ipa_limit()) { 3666 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3667 cpu_die_early(); 3668 } 3669 } 3670 3671 static void verify_mpam_capabilities(void) 3672 { 3673 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3674 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3675 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3676 3677 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3678 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3679 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3680 cpu_die_early(); 3681 } 3682 3683 cpu_idr = read_cpuid(MPAMIDR_EL1); 3684 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3685 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3686 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3687 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3688 cpu_die_early(); 3689 } 3690 3691 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3692 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3693 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3694 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3695 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3696 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3697 cpu_die_early(); 3698 } 3699 } 3700 3701 /* 3702 * Run through the enabled system capabilities and enable() it on this CPU. 3703 * The capabilities were decided based on the available CPUs at the boot time. 3704 * Any new CPU should match the system wide status of the capability. If the 3705 * new CPU doesn't have a capability which the system now has enabled, we 3706 * cannot do anything to fix it up and could cause unexpected failures. So 3707 * we park the CPU. 3708 */ 3709 static void verify_local_cpu_capabilities(void) 3710 { 3711 /* 3712 * The capabilities with SCOPE_BOOT_CPU are checked from 3713 * check_early_cpu_features(), as they need to be verified 3714 * on all secondary CPUs. 3715 */ 3716 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3717 verify_local_elf_hwcaps(); 3718 3719 if (system_supports_sve()) 3720 verify_sve_features(); 3721 3722 if (system_supports_sme()) 3723 verify_sme_features(); 3724 3725 if (is_hyp_mode_available()) 3726 verify_hyp_capabilities(); 3727 3728 if (system_supports_mpam()) 3729 verify_mpam_capabilities(); 3730 } 3731 3732 void check_local_cpu_capabilities(void) 3733 { 3734 /* 3735 * All secondary CPUs should conform to the early CPU features 3736 * in use by the kernel based on boot CPU. 3737 */ 3738 check_early_cpu_features(); 3739 3740 /* 3741 * If we haven't finalised the system capabilities, this CPU gets 3742 * a chance to update the errata work arounds and local features. 3743 * Otherwise, this CPU should verify that it has all the system 3744 * advertised capabilities. 3745 */ 3746 if (!system_capabilities_finalized()) 3747 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3748 else 3749 verify_local_cpu_capabilities(); 3750 } 3751 3752 bool this_cpu_has_cap(unsigned int n) 3753 { 3754 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3755 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3756 3757 if (cap) 3758 return cap->matches(cap, SCOPE_LOCAL_CPU); 3759 } 3760 3761 return false; 3762 } 3763 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3764 3765 /* 3766 * This helper function is used in a narrow window when, 3767 * - The system wide safe registers are set with all the SMP CPUs and, 3768 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3769 */ 3770 static bool __maybe_unused __system_matches_cap(unsigned int n) 3771 { 3772 if (n < ARM64_NCAPS) { 3773 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3774 3775 if (cap) 3776 return cap->matches(cap, SCOPE_SYSTEM); 3777 } 3778 return false; 3779 } 3780 3781 void cpu_set_feature(unsigned int num) 3782 { 3783 set_bit(num, elf_hwcap); 3784 } 3785 3786 bool cpu_have_feature(unsigned int num) 3787 { 3788 return test_bit(num, elf_hwcap); 3789 } 3790 EXPORT_SYMBOL_GPL(cpu_have_feature); 3791 3792 unsigned long cpu_get_elf_hwcap(void) 3793 { 3794 /* 3795 * We currently only populate the first 32 bits of AT_HWCAP. Please 3796 * note that for userspace compatibility we guarantee that bits 62 3797 * and 63 will always be returned as 0. 3798 */ 3799 return elf_hwcap[0]; 3800 } 3801 3802 unsigned long cpu_get_elf_hwcap2(void) 3803 { 3804 return elf_hwcap[1]; 3805 } 3806 3807 unsigned long cpu_get_elf_hwcap3(void) 3808 { 3809 return elf_hwcap[2]; 3810 } 3811 3812 static void __init setup_boot_cpu_capabilities(void) 3813 { 3814 kvm_arm_target_impl_cpu_init(); 3815 /* 3816 * The boot CPU's feature register values have been recorded. Detect 3817 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3818 * patch alternatives for the available boot cpucaps. 3819 */ 3820 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3821 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3822 apply_boot_alternatives(); 3823 } 3824 3825 void __init setup_boot_cpu_features(void) 3826 { 3827 /* 3828 * Initialize the indirect array of CPU capabilities pointers before we 3829 * handle the boot CPU. 3830 */ 3831 init_cpucap_indirect_list(); 3832 3833 /* 3834 * Detect broken pseudo-NMI. Must be called _before_ the call to 3835 * setup_boot_cpu_capabilities() since it interacts with 3836 * can_use_gic_priorities(). 3837 */ 3838 detect_system_supports_pseudo_nmi(); 3839 3840 setup_boot_cpu_capabilities(); 3841 } 3842 3843 static void __init setup_system_capabilities(void) 3844 { 3845 /* 3846 * The system-wide safe feature register values have been finalized. 3847 * Detect, enable, and patch alternatives for the available system 3848 * cpucaps. 3849 */ 3850 update_cpu_capabilities(SCOPE_SYSTEM); 3851 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3852 apply_alternatives_all(); 3853 3854 for (int i = 0; i < ARM64_NCAPS; i++) { 3855 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3856 3857 if (!caps || !caps->desc) 3858 continue; 3859 3860 /* 3861 * Log any cpucaps with a cpumask as these aren't logged by 3862 * update_cpu_capabilities(). 3863 */ 3864 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3865 pr_info("detected: %s on CPU%*pbl\n", 3866 caps->desc, cpumask_pr_args(caps->cpus)); 3867 3868 /* Log match-all CPUs capabilities */ 3869 if (cpucap_match_all_early_cpus(caps) && 3870 cpus_have_cap(caps->capability)) 3871 pr_info("detected: %s\n", caps->desc); 3872 } 3873 3874 /* 3875 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3876 */ 3877 if (system_uses_ttbr0_pan()) 3878 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3879 3880 /* 3881 * Report Spectre mitigations status. 3882 */ 3883 spectre_print_disabled_mitigations(); 3884 } 3885 3886 void __init setup_system_features(void) 3887 { 3888 setup_system_capabilities(); 3889 3890 linear_map_maybe_split_to_ptes(); 3891 kpti_install_ng_mappings(); 3892 3893 sve_setup(); 3894 sme_setup(); 3895 3896 /* 3897 * Check for sane CTR_EL0.CWG value. 3898 */ 3899 if (!cache_type_cwg()) 3900 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3901 ARCH_DMA_MINALIGN); 3902 } 3903 3904 void __init setup_user_features(void) 3905 { 3906 user_feature_fixup(); 3907 3908 setup_elf_hwcaps(arm64_elf_hwcaps); 3909 3910 if (system_supports_32bit_el0()) { 3911 setup_elf_hwcaps(compat_elf_hwcaps); 3912 elf_hwcap_fixup(); 3913 } 3914 3915 minsigstksz_setup(); 3916 } 3917 3918 static int enable_mismatched_32bit_el0(unsigned int cpu) 3919 { 3920 /* 3921 * The first 32-bit-capable CPU we detected and so can no longer 3922 * be offlined by userspace. -1 indicates we haven't yet onlined 3923 * a 32-bit-capable CPU. 3924 */ 3925 static int lucky_winner = -1; 3926 3927 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3928 bool cpu_32bit = false; 3929 3930 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3931 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3932 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3933 else 3934 cpu_32bit = true; 3935 } 3936 3937 if (cpu_32bit) { 3938 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3939 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3940 } 3941 3942 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3943 return 0; 3944 3945 if (lucky_winner >= 0) 3946 return 0; 3947 3948 /* 3949 * We've detected a mismatch. We need to keep one of our CPUs with 3950 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3951 * every CPU in the system for a 32-bit task. 3952 */ 3953 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3954 cpu_active_mask); 3955 get_cpu_device(lucky_winner)->offline_disabled = true; 3956 setup_elf_hwcaps(compat_elf_hwcaps); 3957 elf_hwcap_fixup(); 3958 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3959 cpu, lucky_winner); 3960 return 0; 3961 } 3962 3963 static int __init init_32bit_el0_mask(void) 3964 { 3965 if (!allow_mismatched_32bit_el0) 3966 return 0; 3967 3968 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3969 return -ENOMEM; 3970 3971 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3972 "arm64/mismatched_32bit_el0:online", 3973 enable_mismatched_32bit_el0, NULL); 3974 } 3975 subsys_initcall_sync(init_32bit_el0_mask); 3976 3977 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3978 { 3979 cpu_enable_swapper_cnp(); 3980 } 3981 3982 /* 3983 * We emulate only the following system register space. 3984 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3985 * See Table C5-6 System instruction encodings for System register accesses, 3986 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3987 */ 3988 static inline bool __attribute_const__ is_emulated(u32 id) 3989 { 3990 return (sys_reg_Op0(id) == 0x3 && 3991 sys_reg_CRn(id) == 0x0 && 3992 sys_reg_Op1(id) == 0x0 && 3993 (sys_reg_CRm(id) == 0 || 3994 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3995 } 3996 3997 /* 3998 * With CRm == 0, reg should be one of : 3999 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4000 */ 4001 static inline int emulate_id_reg(u32 id, u64 *valp) 4002 { 4003 switch (id) { 4004 case SYS_MIDR_EL1: 4005 *valp = read_cpuid_id(); 4006 break; 4007 case SYS_MPIDR_EL1: 4008 *valp = SYS_MPIDR_SAFE_VAL; 4009 break; 4010 case SYS_REVIDR_EL1: 4011 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4012 *valp = 0; 4013 break; 4014 default: 4015 return -EINVAL; 4016 } 4017 4018 return 0; 4019 } 4020 4021 static int emulate_sys_reg(u32 id, u64 *valp) 4022 { 4023 struct arm64_ftr_reg *regp; 4024 4025 if (!is_emulated(id)) 4026 return -EINVAL; 4027 4028 if (sys_reg_CRm(id) == 0) 4029 return emulate_id_reg(id, valp); 4030 4031 regp = get_arm64_ftr_reg_nowarn(id); 4032 if (regp) 4033 *valp = arm64_ftr_reg_user_value(regp); 4034 else 4035 /* 4036 * The untracked registers are either IMPLEMENTATION DEFINED 4037 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4038 */ 4039 *valp = 0; 4040 return 0; 4041 } 4042 4043 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4044 { 4045 int rc; 4046 u64 val; 4047 4048 rc = emulate_sys_reg(sys_reg, &val); 4049 if (!rc) { 4050 pt_regs_write_reg(regs, rt, val); 4051 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4052 } 4053 return rc; 4054 } 4055 4056 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4057 { 4058 u32 sys_reg, rt; 4059 4060 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4061 return false; 4062 4063 /* 4064 * sys_reg values are defined as used in mrs/msr instruction. 4065 * shift the imm value to get the encoding. 4066 */ 4067 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4068 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4069 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4070 } 4071 4072 enum mitigation_state arm64_get_meltdown_state(void) 4073 { 4074 if (__meltdown_safe) 4075 return SPECTRE_UNAFFECTED; 4076 4077 if (arm64_kernel_unmapped_at_el0()) 4078 return SPECTRE_MITIGATED; 4079 4080 return SPECTRE_VULNERABLE; 4081 } 4082 4083 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4084 char *buf) 4085 { 4086 switch (arm64_get_meltdown_state()) { 4087 case SPECTRE_UNAFFECTED: 4088 return sprintf(buf, "Not affected\n"); 4089 4090 case SPECTRE_MITIGATED: 4091 return sprintf(buf, "Mitigation: PTI\n"); 4092 4093 default: 4094 return sprintf(buf, "Vulnerable\n"); 4095 } 4096 }