Linux v6.18.37 · 원본 파일 · 온라인 원본
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Macros for accessing system registers with older binutils.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <[email protected]>
7 */
8
9#ifndef __ASM_SYSREG_H
10#define __ASM_SYSREG_H
11
12#include <linux/bits.h>
13#include <linux/stringify.h>
14#include <linux/kasan-tags.h>
15#include <linux/kconfig.h>
16
17#include <asm/gpr-num.h>
18
19/*
20 * ARMv8 ARM reserves the following encoding for system registers:
21 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
22 * C5.2, version:ARM DDI 0487A.f)
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
28 */
29#define Op0_shift 19
30#define Op0_mask 0x3
31#define Op1_shift 16
32#define Op1_mask 0x7
33#define CRn_shift 12
34#define CRn_mask 0xf
35#define CRm_shift 8
36#define CRm_mask 0xf
37#define Op2_shift 5
38#define Op2_mask 0x7
39
40#define sys_reg(op0, op1, crn, crm, op2) \
41 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
42 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
43 ((op2) << Op2_shift))
44
45#define sys_insn sys_reg
46
47#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
48#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
49#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
50#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
51#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
52
53#ifndef CONFIG_BROKEN_GAS_INST
54
55#ifdef __ASSEMBLY__
56// The space separator is omitted so that __emit_inst(x) can be parsed as
57// either an assembler directive or an assembler macro argument.
58#define __emit_inst(x) .inst(x)
59#else
60#define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
61#endif
62
63#else /* CONFIG_BROKEN_GAS_INST */
64
65#ifndef CONFIG_CPU_BIG_ENDIAN
66#define __INSTR_BSWAP(x) (x)
67#else /* CONFIG_CPU_BIG_ENDIAN */
68#define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
69 (((x) << 8) & 0x00ff0000) | \
70 (((x) >> 8) & 0x0000ff00) | \
71 (((x) >> 24) & 0x000000ff))
72#endif /* CONFIG_CPU_BIG_ENDIAN */
73
74#ifdef __ASSEMBLY__
75#define __emit_inst(x) .long __INSTR_BSWAP(x)
76#else /* __ASSEMBLY__ */
77#define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
78#endif /* __ASSEMBLY__ */
79
80#endif /* CONFIG_BROKEN_GAS_INST */
81
82/*
83 * Instructions for modifying PSTATE fields.
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
85 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
86 * for accessing PSTATE fields have the following encoding:
87 * Op0 = 0, CRn = 4
88 * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
89 * CRm = Imm4 for the instruction.
90 * Rt = 0x1f
91 */
92#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
93#define PSTATE_Imm_shift CRm_shift
94#define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
95
96#define PSTATE_PAN pstate_field(0, 4)
97#define PSTATE_UAO pstate_field(0, 3)
98#define PSTATE_SSBS pstate_field(3, 1)
99#define PSTATE_DIT pstate_field(3, 2)
100#define PSTATE_TCO pstate_field(3, 4)
101
102#define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN)
103#define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO)
104#define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS)
105#define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT)
106#define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO)
107
108#define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x))
109#define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x))
110#define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
111#define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x))
112
113/* Register-based PAN access, for save/restore purposes */
114#define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
115
116#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \
117 __emit_inst(0xd5000000 | \
118 sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \
119 ((Rt) & 0x1f))
120
121#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
122#define GSB_SYS_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)
123#define GSB_ACK_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)
124
125/* Data cache zero operations */
126#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
127#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
128#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
129#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
130#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
131#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
132#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
133#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
134#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
135
136#define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
137#define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
138#define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
139
140#define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
141#define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
142#define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
143
144#define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
145#define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
146#define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
147
148#define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
149
150#define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
151#define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
152#define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
153
154#define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
155#define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
156#define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
157
158#define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
159#define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
160#define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
161
162#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
163#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
164#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
165
166#define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
167#define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
168
169/*
170 * Automatically generated definitions for system registers, the
171 * manual encodings below are in the process of being converted to
172 * come from here. The header relies on the definition of sys_reg()
173 * earlier in this file.
174 */
175#include "asm/sysreg-defs.h"
176
177/*
178 * System registers, organised loosely by encoding but grouped together
179 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
180 */
181#define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
182#define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
183#define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
184
185#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
186#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
187#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
188#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
189#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
190
191#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
192#define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
193#define OSLSR_EL1_OSLM_NI 0
194#define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
195#define OSLSR_EL1_OSLK BIT(1)
196
197#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
198#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
199#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
200#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
201#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
202#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
203#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
204#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
205#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
206#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
207
208#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
209#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
210#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
211
212#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
213#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
216#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
217#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
218#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
219#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
220#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
221#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
228#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
230#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
235#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
236#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
237#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
245#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
246#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
247#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
248#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
249#define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
250#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
251#define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
252#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
253#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
254#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
255#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
256#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
260#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
261#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
262#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
263#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
264#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
265#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
266#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
267#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
268#define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
269#define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
270#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
271#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
272
273/* ETM */
274#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
275
276#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
277#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
278#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
279
280#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
281#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
282#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
283
284#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
285#define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
286#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
287#define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
288
289#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
290#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
291#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
292#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
293
294#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
295#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
296
297#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
298#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
299
300#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
301
302#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
303#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
304#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
305
306#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
307#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
308#define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
309#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
310#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
311#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
312#define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
313#define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
314#define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
315#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
316#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
317#define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
318#define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
319#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
320#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
321
322#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
323
324#define SYS_PAR_EL1_F BIT(0)
325/* When PAR_EL1.F == 1 */
326#define SYS_PAR_EL1_FST GENMASK(6, 1)
327#define SYS_PAR_EL1_PTW BIT(8)
328#define SYS_PAR_EL1_S BIT(9)
329#define SYS_PAR_EL1_AssuredOnly BIT(12)
330#define SYS_PAR_EL1_TopLevel BIT(13)
331#define SYS_PAR_EL1_Overlay BIT(14)
332#define SYS_PAR_EL1_DirtyBit BIT(15)
333#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)
334#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
335#define SYS_PAR_EL1_RES1 BIT(11)
336/* When PAR_EL1.F == 0 */
337#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
338#define SYS_PAR_EL1_NS BIT(9)
339#define SYS_PAR_EL1_F0_IMPDEF BIT(10)
340#define SYS_PAR_EL1_NSE BIT(11)
341#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)
342#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)
343#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
344
345/* Buffer error reporting */
346#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
347#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK
348
349#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT
350#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK
351
352#define PMBSR_EL1_BUF_BSC_FULL 0x1UL
353
354/*** End of Statistical Profiling Extension ***/
355
356#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
357#define TRBSR_EL1_BSC_SHIFT 0
358
359#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
360#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
361
362#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
363
364#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
365#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
366
367#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
368#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
369
370#define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
371#define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
372#define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
373#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
374#define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
375#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
376#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
377#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
378#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
379#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
380#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
381#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
382#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
383#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
384#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
385#define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
386#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
387#define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
388#define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
389#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
390#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
391#define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
392#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
393#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
394#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
395#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
396#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
397
398#define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
399
400#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
401
402#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
403
404#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
405#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
406
407#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
408#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
409#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
410#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
411#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
412#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
413#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
414#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
415#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
416#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
417#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
418#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
419
420#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
421#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
422#define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
423
424#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
425
426/* Definitions for system register interface to AMU for ARMv8.4 onwards */
427#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
428#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
429#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
430#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
431#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
432#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
433#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
434#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
435#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
436
437/*
438 * Group 0 of activity monitors (architected):
439 * op0 op1 CRn CRm op2
440 * Counter: 11 011 1101 010:n<3> n<2:0>
441 * Type: 11 011 1101 011:n<3> n<2:0>
442 * n: 0-15
443 *
444 * Group 1 of activity monitors (auxiliary):
445 * op0 op1 CRn CRm op2
446 * Counter: 11 011 1101 110:n<3> n<2:0>
447 * Type: 11 011 1101 111:n<3> n<2:0>
448 * n: 0-15
449 */
450
451#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
452#define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
453#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
454#define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
455
456/* AMU v1: Fixed (architecturally defined) activity monitors */
457#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
458#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
459#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
460#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
461
462#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
463
464#define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
465#define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
466#define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
467#define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
468
469#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
470#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
471#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
472
473#define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
474#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
475#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
476
477#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
478#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
479#define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
480#define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0)
481#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
482#define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
483#define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0)
484
485#define __PMEV_op2(n) ((n) & 0x7)
486#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
487#define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
488#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
489#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
490#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
491
492#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
493
494#define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
495
496#define __SPMEV_op2(n) ((n) & 0x7)
497#define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
498#define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
499#define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
500#define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
501#define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
502
503#define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
504#define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
505
506#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
507#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
508#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
509#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
510#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
511#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
512#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
513#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
514
515#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
516#define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
517#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
518#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
519#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
520
521#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
522#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
523#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
524#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
525#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
526#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
527#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
528#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
529#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
530#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
531#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
532#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
533#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
534#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
535#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
536
537#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
538#define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
539
540#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
541#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
542
543#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
544#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
545#define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
546#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
547#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
548#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
549#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
550#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
551#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
552
553#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
554#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
555#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
556#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
557#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
558
559#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
561#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
562#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
563#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
564
565#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
566#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
567#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
568#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
569#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
570#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
571#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
572#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
573#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
574
575#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
576#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
577#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
578#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
579#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
580#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
581#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
582#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
583#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
584
585#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
586#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
587#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
588
589#define __AMEV_op2(m) (m & 0x7)
590#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
591#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
592#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
593#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
594#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
595
596#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
597#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
598#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
599#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
600#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
601#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
602#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
603#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
604
605/* VHE encodings for architectural EL0/1 system registers */
606#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
607#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
608#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
609#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
610#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
611#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
612#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
613#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
614#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
615#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
616#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
617#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
618#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
619#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
620#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
621#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
622#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
623#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
624#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
625#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
626#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
627
628#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
629
630/* AT instructions */
631#define AT_Op0 1
632#define AT_CRn 7
633
634#define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
635#define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
636#define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
637#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
638#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
639#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
640#define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
641#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
642#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
643#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
644#define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
645#define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
646#define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
647#define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
648
649/* TLBI instructions */
650#define TLBI_Op0 1
651
652#define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */
653#define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */
654
655#define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
656#define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
657
658#define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
659#define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
660#define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
661#define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
662#define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
663#define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
664#define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
665#define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
666
667#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
668#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
669#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
670#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
671#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
672#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
673#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
674#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
675#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
676#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
677#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
678#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
679#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
680#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
681#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
682#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
683#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
684#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
685#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
686#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
687#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
688#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
689#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
690#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
691#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
692#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
693#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
694#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
695#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
696#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
697#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
698#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
699#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
700#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
701#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
702#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
703#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
704#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
705#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
706#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
707#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
708#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
709#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
710#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
711#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
712#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
713#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
714#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
715#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
716#define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
717#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
718#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
719#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
720#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
721#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
722#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
723#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
724#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
725#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
726#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
727#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
728#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
729#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
730#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
731#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
732#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
733#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
734#define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
735#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
736#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
737#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
738#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
739#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
740#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
741#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
742#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
743#define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
744#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
745#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
746#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
747#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
748#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
749#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
750#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
751#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
752#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
753#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
754#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
755#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
756#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
757#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
758#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
759#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
760#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
761#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
762#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
763#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
764#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
765#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
766#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
767#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
768#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
769#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
770#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
771#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
772#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
773#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
774#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
775#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
776#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
777#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
778#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
779#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
780#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
781#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
782#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
783#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
784#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
785#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
786#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
787#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
788#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
789#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
790#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
791#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
792#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
793
794/* Misc instructions */
795#define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
796#define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
797#define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
798#define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
799
800#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
801#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
802#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
803#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
804#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
805#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
806
807/*
808 * BRBE Instructions
809 */
810#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
811#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
812
813/* Common SCTLR_ELx flags. */
814#define SCTLR_ELx_ENTP2 (BIT(60))
815#define SCTLR_ELx_DSSBS (BIT(44))
816#define SCTLR_ELx_ATA (BIT(43))
817
818#define SCTLR_ELx_EE_SHIFT 25
819#define SCTLR_ELx_ENIA_SHIFT 31
820
821#define SCTLR_ELx_ITFSB (BIT(37))
822#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
823#define SCTLR_ELx_ENIB (BIT(30))
824#define SCTLR_ELx_LSMAOE (BIT(29))
825#define SCTLR_ELx_nTLSMD (BIT(28))
826#define SCTLR_ELx_ENDA (BIT(27))
827#define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
828#define SCTLR_ELx_EIS (BIT(22))
829#define SCTLR_ELx_IESB (BIT(21))
830#define SCTLR_ELx_TSCXT (BIT(20))
831#define SCTLR_ELx_WXN (BIT(19))
832#define SCTLR_ELx_ENDB (BIT(13))
833#define SCTLR_ELx_I (BIT(12))
834#define SCTLR_ELx_EOS (BIT(11))
835#define SCTLR_ELx_SA (BIT(3))
836#define SCTLR_ELx_C (BIT(2))
837#define SCTLR_ELx_A (BIT(1))
838#define SCTLR_ELx_M (BIT(0))
839
840/* SCTLR_EL2 specific flags. */
841#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
842 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
843 (BIT(29)))
844
845#define SCTLR_EL2_BT (BIT(36))
846#ifdef CONFIG_CPU_BIG_ENDIAN
847#define ENDIAN_SET_EL2 SCTLR_ELx_EE
848#else
849#define ENDIAN_SET_EL2 0
850#endif
851
852#define INIT_SCTLR_EL2_MMU_ON \
853 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
854 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \
855 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
856
857#define INIT_SCTLR_EL2_MMU_OFF \
858 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
859
860/* SCTLR_EL1 specific flags. */
861#ifdef CONFIG_CPU_BIG_ENDIAN
862#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
863#else
864#define ENDIAN_SET_EL1 0
865#endif
866
867#define INIT_SCTLR_EL1_MMU_OFF \
868 (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
869 SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
870
871#define INIT_SCTLR_EL1_MMU_ON \
872 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
873 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \
874 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \
875 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
876 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \
877 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \
878 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
879
880/* MAIR_ELx memory attributes (used by Linux) */
881#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
882#define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
883#define MAIR_ATTR_NORMAL_NC UL(0x44)
884#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
885#define MAIR_ATTR_NORMAL UL(0xff)
886#define MAIR_ATTR_MASK UL(0xff)
887
888/* Position the attr at the correct index */
889#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
890
891/* id_aa64mmfr0 */
892#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
893#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
894#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
895#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
896#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
897#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
898#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
899#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
900
901#define ARM64_MIN_PARANGE_BITS 32
902
903#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
904#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
905#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
906#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3
907#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
908
909#ifdef CONFIG_ARM64_PA_BITS_52
910#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52
911#else
912#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
913#endif
914
915#if defined(CONFIG_ARM64_4K_PAGES)
916#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
917#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
918#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
919#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
920#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
921#elif defined(CONFIG_ARM64_16K_PAGES)
922#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
923#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
924#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
925#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
926#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
927#elif defined(CONFIG_ARM64_64K_PAGES)
928#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT
929#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
930#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
931#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
932#endif
933
934#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
935#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
936
937#define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
938#define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
939
940#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
941#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
942
943/* GCR_EL1 Definitions */
944#define SYS_GCR_EL1_RRND (BIT(16))
945#define SYS_GCR_EL1_EXCL_MASK 0xffffUL
946
947#ifdef CONFIG_KASAN_HW_TAGS
948/*
949 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
950 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
951 */
952#define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
953#define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
954#define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
955#define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
956#else
957#define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
958#endif
959
960#define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
961
962/* RGSR_EL1 Definitions */
963#define SYS_RGSR_EL1_TAG_MASK 0xfUL
964#define SYS_RGSR_EL1_SEED_SHIFT 8
965#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
966
967/* TFSR{,E0}_EL1 bit definitions */
968#define SYS_TFSR_EL1_TF0_SHIFT 0
969#define SYS_TFSR_EL1_TF1_SHIFT 1
970#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
971#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
972
973/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
974#define SYS_MPIDR_SAFE_VAL (BIT(31))
975
976/* GIC Hypervisor interface registers */
977/* ICH_LR*_EL2 bit definitions */
978#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
979
980#define ICH_LR_EOI (1ULL << 41)
981#define ICH_LR_GROUP (1ULL << 60)
982#define ICH_LR_HW (1ULL << 61)
983#define ICH_LR_STATE (3ULL << 62)
984#define ICH_LR_PENDING_BIT (1ULL << 62)
985#define ICH_LR_ACTIVE_BIT (1ULL << 63)
986#define ICH_LR_PHYS_ID_SHIFT 32
987#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
988#define ICH_LR_PRIORITY_SHIFT 48
989#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
990
991/* ICH_VMCR_EL2 bit definitions */
992#define ICH_VMCR_ACK_CTL_SHIFT 2
993#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
994#define ICH_VMCR_FIQ_EN_SHIFT 3
995#define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
996#define ICH_VMCR_CBPR_SHIFT 4
997#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
998#define ICH_VMCR_EOIM_SHIFT 9
999#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
1000#define ICH_VMCR_BPR1_SHIFT 18
1001#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1002#define ICH_VMCR_BPR0_SHIFT 21
1003#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1004#define ICH_VMCR_PMR_SHIFT 24
1005#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
1006#define ICH_VMCR_ENG0_SHIFT 0
1007#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
1008#define ICH_VMCR_ENG1_SHIFT 1
1009#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
1010
1011/*
1012 * Permission Indirection Extension (PIE) permission encodings.
1013 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
1014 */
1015#define PIE_NONE_O UL(0x0)
1016#define PIE_R_O UL(0x1)
1017#define PIE_X_O UL(0x2)
1018#define PIE_RX_O UL(0x3)
1019#define PIE_RW_O UL(0x5)
1020#define PIE_RWnX_O UL(0x6)
1021#define PIE_RWX_O UL(0x7)
1022#define PIE_R UL(0x8)
1023#define PIE_GCS UL(0x9)
1024#define PIE_RX UL(0xa)
1025#define PIE_RW UL(0xc)
1026#define PIE_RWX UL(0xe)
1027#define PIE_MASK UL(0xf)
1028
1029#define PIRx_ELx_BITS_PER_IDX 4
1030#define PIRx_ELx_PERM_SHIFT(idx) ((idx) * PIRx_ELx_BITS_PER_IDX)
1031#define PIRx_ELx_PERM_PREP(idx, perm) (((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx))
1032
1033/*
1034 * Permission Overlay Extension (POE) permission encodings.
1035 */
1036#define POE_NONE UL(0x0)
1037#define POE_R UL(0x1)
1038#define POE_X UL(0x2)
1039#define POE_RX UL(0x3)
1040#define POE_W UL(0x4)
1041#define POE_RW UL(0x5)
1042#define POE_WX UL(0x6)
1043#define POE_RWX UL(0x7)
1044#define POE_MASK UL(0xf)
1045
1046#define POR_ELx_BITS_PER_IDX 4
1047#define POR_ELx_PERM_SHIFT(idx) ((idx) * POR_ELx_BITS_PER_IDX)
1048#define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK)
1049#define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))
1050
1051/*
1052 * Definitions for Guarded Control Stack
1053 */
1054
1055#define GCS_CAP_ADDR_MASK GENMASK(63, 12)
1056#define GCS_CAP_ADDR_SHIFT 12
1057#define GCS_CAP_ADDR_WIDTH 52
1058#define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x)
1059
1060#define GCS_CAP_TOKEN_MASK GENMASK(11, 0)
1061#define GCS_CAP_TOKEN_SHIFT 0
1062#define GCS_CAP_TOKEN_WIDTH 12
1063#define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x)
1064
1065#define GCS_CAP_VALID_TOKEN 0x1
1066#define GCS_CAP_IN_PROGRESS_TOKEN 0x5
1067
1068#define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
1069 GCS_CAP_VALID_TOKEN)
1070/*
1071 * Definitions for GICv5 instructions
1072 */
1073#define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3)
1074#define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0)
1075#define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0)
1076#define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1)
1077#define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1)
1078#define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7)
1079#define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4)
1080#define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)
1081#define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5)
1082#define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)
1083
1084/* Definitions for GIC CDAFF */
1085#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)
1086#define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29)
1087#define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28)
1088#define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)
1089
1090/* Definitions for GIC CDDI */
1091#define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29)
1092#define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0)
1093
1094/* Definitions for GIC CDDIS */
1095#define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29)
1096#define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r)
1097#define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0)
1098#define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r)
1099
1100/* Definitions for GIC CDEN */
1101#define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29)
1102#define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0)
1103
1104/* Definitions for GIC CDHM */
1105#define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32)
1106#define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29)
1107#define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0)
1108
1109/* Definitions for GIC CDPEND */
1110#define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32)
1111#define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29)
1112#define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0)
1113
1114/* Definitions for GIC CDPRI */
1115#define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35)
1116#define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29)
1117#define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0)
1118
1119/* Definitions for GIC CDRCFG */
1120#define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29)
1121#define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0)
1122
1123/* Definitions for GICR CDIA */
1124#define GICV5_GIC_CDIA_VALID_MASK BIT_ULL(32)
1125#define GICV5_GICR_CDIA_VALID(r) FIELD_GET(GICV5_GIC_CDIA_VALID_MASK, r)
1126#define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29)
1127#define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0)
1128
1129#define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn)
1130#define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn)
1131
1132#define ARM64_FEATURE_FIELD_BITS 4
1133
1134#ifdef __ASSEMBLY__
1135
1136 .macro mrs_s, rt, sreg
1137 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1138 .endm
1139
1140 .macro msr_s, sreg, rt
1141 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1142 .endm
1143
1144 .macro msr_hcr_el2, reg
1145#if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23)
1146 dsb nsh
1147 msr hcr_el2, \reg
1148 isb
1149#else
1150 msr hcr_el2, \reg
1151#endif
1152 .endm
1153#else
1154
1155#include <linux/bitfield.h>
1156#include <linux/build_bug.h>
1157#include <linux/types.h>
1158#include <asm/alternative.h>
1159
1160#define DEFINE_MRS_S \
1161 __DEFINE_ASM_GPR_NUMS \
1162" .macro mrs_s, rt, sreg\n" \
1163 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
1164" .endm\n"
1165
1166#define DEFINE_MSR_S \
1167 __DEFINE_ASM_GPR_NUMS \
1168" .macro msr_s, sreg, rt\n" \
1169 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
1170" .endm\n"
1171
1172#define UNDEFINE_MRS_S \
1173" .purgem mrs_s\n"
1174
1175#define UNDEFINE_MSR_S \
1176" .purgem msr_s\n"
1177
1178#define __mrs_s(v, r) \
1179 DEFINE_MRS_S \
1180" mrs_s " v ", " __stringify(r) "\n" \
1181 UNDEFINE_MRS_S
1182
1183#define __msr_s(r, v) \
1184 DEFINE_MSR_S \
1185" msr_s " __stringify(r) ", " v "\n" \
1186 UNDEFINE_MSR_S
1187
1188/*
1189 * Unlike read_cpuid, calls to read_sysreg are never expected to be
1190 * optimized away or replaced with synthetic values.
1191 */
1192#define read_sysreg(r) ({ \
1193 u64 __val; \
1194 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1195 __val; \
1196})
1197
1198/*
1199 * The "Z" constraint normally means a zero immediate, but when combined with
1200 * the "%x0" template means XZR.
1201 */
1202#define write_sysreg(v, r) do { \
1203 u64 __val = (u64)(v); \
1204 asm volatile("msr " __stringify(r) ", %x0" \
1205 : : "rZ" (__val)); \
1206} while (0)
1207
1208/*
1209 * For registers without architectural names, or simply unsupported by
1210 * GAS.
1211 *
1212 * __check_r forces warnings to be generated by the compiler when
1213 * evaluating r which wouldn't normally happen due to being passed to
1214 * the assembler via __stringify(r).
1215 */
1216#define read_sysreg_s(r) ({ \
1217 u64 __val; \
1218 u32 __maybe_unused __check_r = (u32)(r); \
1219 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1220 __val; \
1221})
1222
1223/*
1224 * The "Z" constraint combined with the "%x0" template should be enough
1225 * to force XZR generation if (v) is a constant 0 value but LLVM does not
1226 * yet understand that modifier/constraint combo so a conditional is required
1227 * to nudge the compiler into using XZR as a source for a 0 constant value.
1228 */
1229#define write_sysreg_s(v, r) do { \
1230 u64 __val = (u64)(v); \
1231 u32 __maybe_unused __check_r = (u32)(r); \
1232 if (__builtin_constant_p(__val) && __val == 0) \
1233 asm volatile(__msr_s(r, "xzr")); \
1234 else \
1235 asm volatile(__msr_s(r, "%x0") : : "r" (__val)); \
1236} while (0)
1237
1238/*
1239 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1240 * set mask are set. Other bits are left as-is.
1241 */
1242#define sysreg_clear_set(sysreg, clear, set) do { \
1243 u64 __scs_val = read_sysreg(sysreg); \
1244 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1245 if (__scs_new != __scs_val) \
1246 write_sysreg(__scs_new, sysreg); \
1247} while (0)
1248
1249#define sysreg_clear_set_hcr(clear, set) do { \
1250 u64 __scs_val = read_sysreg(hcr_el2); \
1251 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1252 if (__scs_new != __scs_val) \
1253 write_sysreg_hcr(__scs_new); \
1254} while (0)
1255
1256#define sysreg_clear_set_s(sysreg, clear, set) do { \
1257 u64 __scs_val = read_sysreg_s(sysreg); \
1258 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1259 if (__scs_new != __scs_val) \
1260 write_sysreg_s(__scs_new, sysreg); \
1261} while (0)
1262
1263#define write_sysreg_hcr(__val) do { \
1264 if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \
1265 (!system_capabilities_finalized() || \
1266 alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23))) \
1267 asm volatile("dsb nsh; msr hcr_el2, %x0; isb" \
1268 : : "rZ" (__val)); \
1269 else \
1270 asm volatile("msr hcr_el2, %x0" \
1271 : : "rZ" (__val)); \
1272} while (0)
1273
1274#define read_sysreg_par() ({ \
1275 u64 par; \
1276 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1277 par = read_sysreg(par_el1); \
1278 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1279 par; \
1280})
1281
1282#define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val
1283
1284#define SYS_FIELD_GET(reg, field, val) \
1285 FIELD_GET(reg##_##field##_MASK, val)
1286
1287#define SYS_FIELD_PREP(reg, field, val) \
1288 FIELD_PREP(reg##_##field##_MASK, val)
1289
1290#define SYS_FIELD_PREP_ENUM(reg, field, val) \
1291 FIELD_PREP(reg##_##field##_MASK, \
1292 SYS_FIELD_VALUE(reg, field, val))
1293
1294#endif
1295
1296#endif /* __ASM_SYSREG_H */