요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
1
.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3
==========
4
VBIOS
5
==========
6
This document describes the layout of the VBIOS image which is a series of concatenated
7
images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space and is read
8
by both Boot ROM firmware (also known as IFR or init-from-rom firmware) on the GPU to
9
bootstrap various microcontrollers (PMU, SEC, GSP) with critical initialization before
10
the driver loads, as well as by the nova-core driver in the kernel to boot the GSP.
12
The format of the images in the ROM follow the "BIOS Specification" part of the
13
PCI specification, with Nvidia-specific extensions. The ROM images of type FwSec
14
are the ones that contain Falcon ucode and what we are mainly looking for.
16
As an example, the following are the different image types that can be found in the
17
VBIOS of an Ampere GA102 GPU which is supported by the nova-core driver.
19
- PciAt Image (Type 0x00) - This is the standard PCI BIOS image, whose name
20
likely comes from the "IBM PC/AT" architecture.
22
- EFI Image (Type 0x03) - This is the EFI BIOS image. It contains the UEFI GOP
23
driver that is used to display UEFI graphics output.
25
- First FwSec Image (Type 0xE0) - The first FwSec image (Secure Firmware)
27
- Second FwSec Image (Type 0xE0) - The second FwSec image (Secure Firmware)
28
contains various microcodes (also known as an applications) that do a range
29
of different functions. The FWSEC ucode is run in heavy-secure mode and
30
typically runs directly on the GSP (it could be running on a different
31
designated processor in future generations but as of Ampere, it is the GSP).
32
This firmware then loads other firmware ucodes onto the PMU and SEC2
33
microcontrollers for gfw initialization after GPU reset and before the driver
34
loads (see devinit.rst). The DEVINIT ucode is itself another ucode that is
35
stored in this ROM partition.
37
Once located, the Falcon ucodes have "Application Interfaces" in their data
38
memory (DMEM). For FWSEC, the application interface we use for FWSEC is the
39
"DMEM mapper" interface which is configured to run the "FRTS" command. This
40
command carves out the WPR2 (Write-Protected Region) in VRAM. It then places
41
important power-management data, called 'FRTS', into this region. The WPR2
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region is only accessible to heavy-secure ucode.
44
.. note::
45
It is not clear why FwSec has 2 different partitions in the ROM, but they both
46
are of type 0xE0 and can be identified as such. This could be subject to change
47
in future generations.
49
VBIOS ROM Layout
50
----------------
51
The VBIOS layout is roughly a series of concatenated images laid out as follows::
53
+----------------------------------------------------------------------------+
54
| VBIOS (Starting at ROM_OFFSET: 0x300000) |
55
+----------------------------------------------------------------------------+
56
| +-----------------------------------------------+ |
57
| | PciAt Image (Type 0x00) | |
58
| +-----------------------------------------------+ |
59
| | +-------------------+ | |
60
| | | ROM Header | | |
61
| | | (Signature 0xAA55)| | |
62
| | +-------------------+ | |
63
| | | rom header's pci_data_struct_offset | |
64
| | | points to the PCIR structure | |
65
| | V | |
66
| | +-------------------+ | |
67
| | | PCIR Structure | | |
68
| | | (Signature "PCIR")| | |
69
| | | last_image: 0x80 | | |
70
| | | image_len: size | | |
71
| | | in 512-byte units | | |
72
| | +-------------------+ | |
73
| | | | |
74
| | | NPDE immediately follows PCIR | |
75
| | V | |
76
| | +-------------------+ | |
77
| | | NPDE Structure | | |
78
| | | (Signature "NPDE")| | |
79
| | | last_image: 0x00 | | |
80
| | +-------------------+ | |
81
| | | |
82
| | +-------------------+ | |
83
| | | BIT Header | (Signature scanning | |
84
| | | (Signature "BIT") | provides the location | |
85
| | +-------------------+ of the BIT table) | |
86
| | | header is | |
87
| | | followed by a table of tokens | |
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| | V one of which is for falcon data. | |
89
| | +-------------------+ | |
90
| | | BIT Tokens | | |
91
| | | ______________ | | |
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| | | | Falcon Data | | | |
93
| | | | Token (0x70)|---+------------>------------+--+ |
94
| | | +-------------+ | falcon_data_ptr() | | |
95
| | +-------------------+ | V |
96
| +-----------------------------------------------+ | |
97
| (no gap between images) | |
98
| +-----------------------------------------------+ | |
99
| | EFI Image (Type 0x03) | | |
100
| +-----------------------------------------------+ | |
101
| | Contains the UEFI GOP driver (Graphics Output)| | |
102
| | +-------------------+ | | |
103
| | | ROM Header | | | |
104
| | +-------------------+ | | |
105
| | | PCIR Structure | | | |
106
| | +-------------------+ | | |
107
| | | NPDE Structure | | | |
108
| | +-------------------+ | | |
109
| | | Image data | | | |
110
| | +-------------------+ | | |
111
| +-----------------------------------------------+ | |
112
| (no gap between images) | |
113
| +-----------------------------------------------+ | |
114
| | First FwSec Image (Type 0xE0) | | |
115
| +-----------------------------------------------+ | |
116
| | +-------------------+ | | |
117
| | | ROM Header | | | |
118
| | +-------------------+ | | |
119
| | | PCIR Structure | | | |
120
| | +-------------------+ | | |
121
| | | NPDE Structure | | | |
122
| | +-------------------+ | | |
123
| | | Image data | | | |
124
| | +-------------------+ | | |
125
| +-----------------------------------------------+ | |
126
| (no gap between images) | |
127
| +-----------------------------------------------+ | |
128
| | Second FwSec Image (Type 0xE0) | | |
129
| +-----------------------------------------------+ | |
130
| | +-------------------+ | | |
131
| | | ROM Header | | | |
132
| | +-------------------+ | | |
133
| | | PCIR Structure | | | |
134
| | +-------------------+ | | |
135
| | | NPDE Structure | | | |
136
| | +-------------------+ | | |
137
| | | | |
138
| | +-------------------+ | | |
139
| | | PMU Lookup Table | <- falcon_data_offset <----+ |
140
| | | +-------------+ | pmu_lookup_table | |
141
| | | | Entry 0x85 | | | |
142
| | | | FWSEC_PROD | | | |
143
| | | +-------------+ | | |
144
| | +-------------------+ | |
145
| | | | |
146
| | | points to | |
147
| | V | |
148
| | +-------------------+ | |
149
| | | FalconUCodeDescV3 | <- falcon_ucode_offset | |
150
| | | (FWSEC Firmware) | fwsec_header() | |
151
| | +-------------------+ | |
152
| | | immediately followed by... | |
153
| | V | |
154
| | +----------------------------+ | |
155
| | | Signatures + FWSEC Ucode | | |
156
| | | fwsec_sigs(), fwsec_ucode()| | |
157
| | +----------------------------+ | |
158
| +-----------------------------------------------+ |
159
| |
160
+----------------------------------------------------------------------------+
162
.. note::
163
This diagram is created based on an GA-102 Ampere GPU as an example and could
164
vary for future or other GPUs.
166
.. note::
167
For more explanations of acronyms, see the detailed descriptions in `vbios.rs`.
169
Falcon data Lookup
170
------------------
171
A key part of the VBIOS extraction code (vbios.rs) is to find the location of the
172
Falcon data in the VBIOS which contains the PMU lookup table. This lookup table is
173
used to find the required Falcon ucode based on an application ID.
175
The location of the PMU lookup table is found by scanning the BIT (`BIOS Information Table`_)
176
tokens for a token with the id `BIT_TOKEN_ID_FALCON_DATA` (0x70) which indicates the
177
offset of the same from the start of the VBIOS image. Unfortunately, the offset
178
does not account for the EFI image located between the PciAt and FwSec images.
179
The `vbios.rs` code compensates for this with appropriate arithmetic.
181
.. _`BIOS Information Table`: https://download.nvidia.com/open-gpu-doc/BIOS-Information-Table/1/BIOS-Information-Table.html
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
VBIOS image와 Ampere ROM type
1-48VBIOS image는 GPU ROM 안에 여러 image를 연속으로 이어 붙인 layout입니다. VBIOS는 BAR 0 space에 mirror되며, GPU의 Boot ROM firmware(IFR, init-from-rom firmware)와 kernel의 `nova-core` driver가 모두 읽습니다. 원문 SPDX 라이선스는 `(GPL-2.0+ OR MIT)`입니다.
Boot ROM firmware는 driver가 load되기 전에 PMU·SEC·GSP microcontroller를 bootstrap하여 핵심 초기화를 수행합니다. Nova-core driver는 이후 GSP를 boot하기 위해 같은 VBIOS를 읽습니다.
ROM image format은 PCI specification의 BIOS Specification을 따르되 NVIDIA-specific extension을 포함합니다. Nova-core가 주로 찾는 것은 Falcon ucode가 들어 있는 FwSec type image입니다.
Ampere GA102 예에서 `PciAt Image (0x00)`은 표준 PCI BIOS image이며 이름은 IBM PC/AT architecture에서 유래한 것으로 보입니다. `EFI Image (0x03)`에는 UEFI graphics output을 표시하는 UEFI GOP driver가 들어 있습니다.
두 `FwSec Image (0xE0)`가 있으며 두 번째 partition은 여러 microcode application을 담습니다. FWSEC ucode는 heavy-secure mode로 보통 GSP에서 직접 실행되고, GPU reset 뒤 driver load 전에 gfw initialization을 위해 PMU·SEC2에 다른 firmware ucode를 load합니다. DEVINIT ucode도 이 ROM partition에 저장됩니다.
Falcon ucode를 찾으면 DMEM 안의 Application Interface를 사용합니다. FWSEC에서는 `DMEM mapper` interface를 설정해 `FRTS` command를 실행합니다. FRTS는 VRAM의 write-protected `WPR2` region을 carve out하고 중요한 power-management data인 FRTS를 넣습니다. WPR2는 heavy-secure ucode만 접근할 수 있습니다.
FwSec partition이 두 개인 이유는 명확하지 않지만 둘 다 type `0xE0`으로 식별합니다. 이 layout은 미래 generation에서 바뀔 수 있습니다.
ImageType내용
PciAt0x00표준 PCI BIOS image
EFI0x03UEFI GOP graphics driver
First FwSec0xE0Secure firmware image
Second FwSec0xE0FWSEC·DEVINIT 등 Falcon ucode application
GA102 ROM에서 확인되는 연속 image입니다.
GPU reset→Boot ROM/IFR가 VBIOS에서 PMU·SEC·GSP firmware bootstrap→FWSEC heavy-secure가 DEVINIT·gfw 초기화→Kernel nova-core driver load→Nova-core가 VBIOS를 다시 읽어 GSP boot·FRTS 수행
Boot ROM과 kernel driver가 같은 ROM을 다른 단계에서 읽습니다.
.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
==========
VBIOS
==========
This document describes the layout of the VBIOS image which is a series of concatenated
images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space and is read
by both Boot ROM firmware (also known as IFR or init-from-rom firmware) on the GPU to
bootstrap various microcontrollers (PMU, SEC, GSP) with critical initialization before
the driver loads, as well as by the nova-core driver in the kernel to boot the GSP.
The format of the images in the ROM follow the "BIOS Specification" part of the
PCI specification, with Nvidia-specific extensions. The ROM images of type FwSec
are the ones that contain Falcon ucode and what we are mainly looking for.
As an example, the following are the different image types that can be found in the
VBIOS of an Ampere GA102 GPU which is supported by the nova-core driver.
- PciAt Image (Type 0x00) - This is the standard PCI BIOS image, whose name
likely comes from the "IBM PC/AT" architecture.
- EFI Image (Type 0x03) - This is the EFI BIOS image. It contains the UEFI GOP
driver that is used to display UEFI graphics output.
- First FwSec Image (Type 0xE0) - The first FwSec image (Secure Firmware)
- Second FwSec Image (Type 0xE0) - The second FwSec image (Secure Firmware)
contains various microcodes (also known as an applications) that do a range
of different functions. The FWSEC ucode is run in heavy-secure mode and
typically runs directly on the GSP (it could be running on a different
designated processor in future generations but as of Ampere, it is the GSP).
This firmware then loads other firmware ucodes onto the PMU and SEC2
microcontrollers for gfw initialization after GPU reset and before the driver
loads (see devinit.rst). The DEVINIT ucode is itself another ucode that is
stored in this ROM partition.
Once located, the Falcon ucodes have "Application Interfaces" in their data
memory (DMEM). For FWSEC, the application interface we use for FWSEC is the
"DMEM mapper" interface which is configured to run the "FRTS" command. This
command carves out the WPR2 (Write-Protected Region) in VRAM. It then places
important power-management data, called 'FRTS', into this region. The WPR2
region is only accessible to heavy-secure ucode.
.. note::
It is not clear why FwSec has 2 different partitions in the ROM, but they both
are of type 0xE0 and can be identified as such. This could be subject to change
in future generations.
VBIOS ROM layout
49-168VBIOS는 `ROM_OFFSET 0x300000`에서 시작하며 PciAt, EFI, First FwSec, Second FwSec image가 gap 없이 이어집니다.
PciAt image의 ROM Header는 signature `0xAA55`와 `pci_data_struct_offset`을 가지며, 이 offset이 signature `PCIR`인 structure를 가리킵니다. PCIR의 `image_len`은 512-byte unit으로 image size를 기록하고 `last_image` 값은 `0x80`입니다.
`NPDE` structure는 PCIR 바로 뒤에 오고 signature `NPDE`, `last_image 0x00`을 가집니다. Signature scan으로 `BIT` header 위치를 찾으며, BIT header 뒤 token table의 Falcon Data Token `0x70`이 Falcon data pointer를 제공합니다.
EFI image는 ROM Header·PCIR·NPDE·image data를 포함하고 UEFI GOP driver를 담습니다. First FwSec image도 ROM Header·PCIR·NPDE·image data 구조를 따릅니다.
Second FwSec image에는 ROM Header·PCIR·NPDE 뒤 `PMU Lookup Table`이 있습니다. PciAt의 BIT Falcon Data Token에서 얻은 `falcon_data_offset`이 이 table을 가리킵니다.
PMU lookup의 entry `0x85 FWSEC_PROD`가 `FalconUCodeDescV3` FWSEC firmware descriptor를 가리킵니다. Descriptor 바로 뒤에는 signature와 FWSEC ucode가 붙으며 `fwsec_sigs()`와 `fwsec_ucode()`가 접근합니다.
이 구조도는 GA-102 Ampere 예를 기반으로 하므로 다른 GPU나 미래 GPU에서는 달라질 수 있습니다. Acronym의 자세한 설명은 `vbios.rs`에 있습니다.
ROM_OFFSET 0x300000→PciAt Image 0x00→EFI Image 0x03→First FwSec Image 0xE0→Second FwSec Image 0xE0
원문 ASCII 그림의 top-level ROM 순서입니다.
구조Signature·field다음 위치
ROM Header0xAA55·pci_data_struct_offsetPCIR
PCIRPCIR·image_len(512-byte units)·last_image 0x80NPDE
NPDENPDE·last_image 0x00BIT signature scan
BIT HeaderBITToken table
Falcon Data TokenID 0x70falcon_data_ptr()
Falcon data token을 찾기까지의 header chain입니다.
단계구조·symbol
Falcon datafalcon_data_offset·pmu_lookup_table
Application lookupEntry 0x85 FWSEC_PROD
DescriptorFalconUCodeDescV3·falcon_ucode_offset·fwsec_header()
PayloadSignatures + FWSEC Ucode
Accessorsfwsec_sigs()·fwsec_ucode()
Falcon data offset에서 ucode payload까지의 구조입니다.
PciAt BIT Token 0x70→falcon_data_ptr()→Second FwSec PMU Lookup Table→Entry 0x85 FWSEC_PROD→FalconUCodeDescV3→Signatures + FWSEC Ucode
PciAt token에서 Second FwSec payload로 건너가는 pointer chain입니다.
VBIOS ROM Layout
----------------
The VBIOS layout is roughly a series of concatenated images laid out as follows::
+----------------------------------------------------------------------------+
| VBIOS (Starting at ROM_OFFSET: 0x300000) |
+----------------------------------------------------------------------------+
| +-----------------------------------------------+ |
| | PciAt Image (Type 0x00) | |
| +-----------------------------------------------+ |
| | +-------------------+ | |
| | | ROM Header | | |
| | | (Signature 0xAA55)| | |
| | +-------------------+ | |
| | | rom header's pci_data_struct_offset | |
| | | points to the PCIR structure | |
| | V | |
| | +-------------------+ | |
| | | PCIR Structure | | |
| | | (Signature "PCIR")| | |
| | | last_image: 0x80 | | |
| | | image_len: size | | |
| | | in 512-byte units | | |
| | +-------------------+ | |
| | | | |
| | | NPDE immediately follows PCIR | |
| | V | |
| | +-------------------+ | |
| | | NPDE Structure | | |
| | | (Signature "NPDE")| | |
| | | last_image: 0x00 | | |
| | +-------------------+ | |
| | | |
| | +-------------------+ | |
| | | BIT Header | (Signature scanning | |
| | | (Signature "BIT") | provides the location | |
| | +-------------------+ of the BIT table) | |
| | | header is | |
| | | followed by a table of tokens | |
| | V one of which is for falcon data. | |
| | +-------------------+ | |
| | | BIT Tokens | | |
| | | ______________ | | |
| | | | Falcon Data | | | |
| | | | Token (0x70)|---+------------>------------+--+ |
| | | +-------------+ | falcon_data_ptr() | | |
| | +-------------------+ | V |
| +-----------------------------------------------+ | |
| (no gap between images) | |
| +-----------------------------------------------+ | |
| | EFI Image (Type 0x03) | | |
| +-----------------------------------------------+ | |
| | Contains the UEFI GOP driver (Graphics Output)| | |
| | +-------------------+ | | |
| | | ROM Header | | | |
| | +-------------------+ | | |
| | | PCIR Structure | | | |
| | +-------------------+ | | |
| | | NPDE Structure | | | |
| | +-------------------+ | | |
| | | Image data | | | |
| | +-------------------+ | | |
| +-----------------------------------------------+ | |
| (no gap between images) | |
| +-----------------------------------------------+ | |
| | First FwSec Image (Type 0xE0) | | |
| +-----------------------------------------------+ | |
| | +-------------------+ | | |
| | | ROM Header | | | |
| | +-------------------+ | | |
| | | PCIR Structure | | | |
| | +-------------------+ | | |
| | | NPDE Structure | | | |
| | +-------------------+ | | |
| | | Image data | | | |
| | +-------------------+ | | |
| +-----------------------------------------------+ | |
| (no gap between images) | |
| +-----------------------------------------------+ | |
| | Second FwSec Image (Type 0xE0) | | |
| +-----------------------------------------------+ | |
| | +-------------------+ | | |
| | | ROM Header | | | |
| | +-------------------+ | | |
| | | PCIR Structure | | | |
| | +-------------------+ | | |
| | | NPDE Structure | | | |
| | +-------------------+ | | |
| | | | |
| | +-------------------+ | | |
| | | PMU Lookup Table | <- falcon_data_offset <----+ |
| | | +-------------+ | pmu_lookup_table | |
| | | | Entry 0x85 | | | |
| | | | FWSEC_PROD | | | |
| | | +-------------+ | | |
| | +-------------------+ | |
| | | | |
| | | points to | |
| | V | |
| | +-------------------+ | |
| | | FalconUCodeDescV3 | <- falcon_ucode_offset | |
| | | (FWSEC Firmware) | fwsec_header() | |
| | +-------------------+ | |
| | | immediately followed by... | |
| | V | |
| | +----------------------------+ | |
| | | Signatures + FWSEC Ucode | | |
| | | fwsec_sigs(), fwsec_ucode()| | |
| | +----------------------------+ | |
| +-----------------------------------------------+ |
| |
+----------------------------------------------------------------------------+
.. note::
This diagram is created based on an GA-102 Ampere GPU as an example and could
vary for future or other GPUs.
.. note::
For more explanations of acronyms, see the detailed descriptions in `vbios.rs`.
Falcon data lookup과 EFI offset 보정
169-181`vbios.rs` extraction code의 핵심은 PMU lookup table이 들어 있는 Falcon data의 VBIOS 내 위치를 찾는 것입니다. 이 table은 application ID를 사용해 필요한 Falcon ucode를 찾습니다.
PMU table 위치는 BIT(BIOS Information Table) token을 scan하여 `BIT_TOKEN_ID_FALCON_DATA (0x70)`를 찾는 방식으로 얻습니다. Token은 VBIOS image 시작점 기준 offset을 나타냅니다.
이 offset은 PciAt image와 FwSec image 사이의 EFI image를 계산에 포함하지 않습니다. 따라서 `vbios.rs`는 적절한 arithmetic으로 EFI image 크기를 보정합니다.
BIOS Information Table의 공개 specification URL은 `https://download.nvidia.com/open-gpu-doc/BIOS-Information-Table/1/BIOS-Information-Table.html`입니다.
PciAt에서 BIT signature scan→BIT_TOKEN_ID_FALCON_DATA 0x70 선택→VBIOS 시작 기준 Falcon data offset 획득→PciAt와 FwSec 사이 EFI image 크기 보정→Second FwSec의 PMU lookup table 접근
BIT token의 불완전한 기준을 EFI 보정으로 실제 위치에 대응시킵니다.
항목값
TokenBIT_TOKEN_ID_FALCON_DATA
Token ID0x70
TablePMU lookup table
FWSEC entryApplication ID 0x85
보정 구현vbios.rs EFI offset arithmetic
Application ID 기반 ucode 검색에 필요한 값입니다.
Falcon data Lookup
------------------
A key part of the VBIOS extraction code (vbios.rs) is to find the location of the
Falcon data in the VBIOS which contains the PMU lookup table. This lookup table is
used to find the required Falcon ucode based on an application ID.
The location of the PMU lookup table is found by scanning the BIT (`BIOS Information Table`_)
tokens for a token with the id `BIT_TOKEN_ID_FALCON_DATA` (0x70) which indicates the
offset of the same from the start of the VBIOS image. Unfortunately, the offset
does not account for the EFI image located between the PciAt and FwSec images.
The `vbios.rs` code compensates for this with appropriate arithmetic.
.. _`BIOS Information Table`: https://download.nvidia.com/open-gpu-doc/BIOS-Information-Table/1/BIOS-Information-Table.html
요약·해설
vbios.rst:1-181Ampere VBIOS image layout과 Falcon ucode·FWSEC lookup을 설명합니다.
Source와 연결 문서입니다.