요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
.. Copyright 2001 Matthew Wilcox
..
.. This documentation is free software; you can redistribute
.. it and/or modify it under the terms of the GNU General Public
.. License as published by the Free Software Foundation; either
.. version 2 of the License, or (at your option) any later
.. version.
===============================
Bus-Independent Device Accesses
===============================
:Author: Matthew Wilcox
:Author: Alan Cox
Introduction
============
Linux provides an API which abstracts performing IO across all buses
and devices, allowing device drivers to be written independently of bus
type.
Memory Mapped IO
================
Getting Access to the Device
----------------------------
The most widely supported form of IO is memory mapped IO. That is, a
part of the CPU's address space is interpreted not as accesses to
memory, but as accesses to a device. Some architectures define devices
to be at a fixed address, but most have some method of discovering
devices. The PCI bus walk is a good example of such a scheme. This
document does not cover how to receive such an address, but assumes you
are starting with one. Physical addresses are of type unsigned long.
This address should not be used directly. Instead, to get an address
suitable for passing to the accessor functions described below, you
should call ioremap(). An address suitable for accessing
the device will be returned to you.
After you've finished using the device (say, in your module's exit
routine), call iounmap() in order to return the address
space to the kernel. Most architectures allocate new address space each
time you call ioremap(), and they can run out unless you
call iounmap().
Accessing the device
--------------------
The part of the interface most used by drivers is reading and writing
memory-mapped registers on the device. Linux provides interfaces to read
and write 8-bit, 16-bit, 32-bit and 64-bit quantities. Due to a
historical accident, these are named byte, word, long and quad accesses.
Both read and write accesses are supported; there is no prefetch support
at this time.
The functions are named readb(), readw(), readl(), readq(),
readb_relaxed(), readw_relaxed(), readl_relaxed(), readq_relaxed(),
writeb(), writew(), writel() and writeq().
Some devices (such as framebuffers) would like to use larger transfers than
8 bytes at a time. For these devices, the memcpy_toio(),
memcpy_fromio() and memset_io() functions are
provided. Do not use memset or memcpy on IO addresses; they are not
guaranteed to copy data in order.
The read and write functions are defined to be ordered. That is the
compiler is not permitted to reorder the I/O sequence. When the ordering
can be compiler optimised, you can use __readb() and friends to
indicate the relaxed ordering. Use this with care.
While the basic functions are defined to be synchronous with respect to
each other and ordered with respect to each other the buses the devices
sit on may themselves have asynchronicity. In particular many authors
are burned by the fact that PCI bus writes are posted asynchronously. A
driver author must issue a read from the same device to ensure that
writes have occurred in the specific cases the author cares. This kind
of property cannot be hidden from driver writers in the API. In some
cases, the read used to flush the device may be expected to fail (if the
card is resetting, for example). In that case, the read should be done
from config space, which is guaranteed to soft-fail if the card doesn't
respond.
The following is an example of flushing a write to a device when the
driver would like to ensure the write's effects are visible prior to
continuing execution::
static inline void
qla1280_disable_intrs(struct scsi_qla_host *ha)
{
struct device_reg *reg;
reg = ha->iobase;
/* disable risc and host interrupts */
WRT_REG_WORD(®->ictrl, 0);
/*
* The following read will ensure that the above write
* has been received by the device before we return from this
* function.
*/
RD_REG_WORD(®->ictrl);
ha->flags.ints_enabled = 0;
}
PCI ordering rules also guarantee that PIO read responses arrive after any
outstanding DMA writes from that bus, since for some devices the result of
a readb() call may signal to the driver that a DMA transaction is
complete. In many cases, however, the driver may want to indicate that the
next readb() call has no relation to any previous DMA writes
performed by the device. The driver can use readb_relaxed() for
these cases, although only some platforms will honor the relaxed
semantics. Using the relaxed read functions will provide significant
performance benefits on platforms that support it. The qla2xxx driver
provides examples of how to use readX_relaxed(). In many cases, a majority
of the driver's readX() calls can safely be converted to readX_relaxed()
calls, since only a few will indicate or depend on DMA completion.
Port Space Accesses
===================
Port Space Explained
--------------------
Another form of IO commonly supported is Port Space. This is a range of
addresses separate to the normal memory address space. Access to these
addresses is generally not as fast as accesses to the memory mapped
addresses, and it also has a potentially smaller address space.
Unlike memory mapped IO, no preparation is required to access port
space.
Accessing Port Space
--------------------
Accesses to this space are provided through a set of functions which
allow 8-bit, 16-bit and 32-bit accesses; also known as byte, word and
long. These functions are inb(), inw(),
inl(), outb(), outw() and
outl().
Some variants are provided for these functions. Some devices require
that accesses to their ports are slowed down. This functionality is
provided by appending a ``_p`` to the end of the function.
There are also equivalents to memcpy. The ins() and
outs() functions copy bytes, words or longs to the given
port.
__iomem pointer tokens
======================
The data type for an MMIO address is an ``__iomem`` qualified pointer, such as
``void __iomem *reg``. On most architectures it is a regular pointer that
points to a virtual memory address and can be offset or dereferenced, but in
portable code, it must only be passed from and to functions that explicitly
operated on an ``__iomem`` token, in particular the ioremap() and
readl()/writel() functions. The 'sparse' semantic code checker can be used to
verify that this is done correctly.
While on most architectures, ioremap() creates a page table entry for an
uncached virtual address pointing to the physical MMIO address, some
architectures require special instructions for MMIO, and the ``__iomem`` pointer
just encodes the physical address or an offsettable cookie that is interpreted
by readl()/writel().
Differences between I/O access functions
========================================
readq(), readl(), readw(), readb(), writeq(), writel(), writew(), writeb()
These are the most generic accessors, providing serialization against other
MMIO accesses and DMA accesses as well as fixed endianness for accessing
little-endian PCI devices and on-chip peripherals. Portable device drivers
should generally use these for any access to ``__iomem`` pointers.
Note that posted writes are not strictly ordered against a spinlock, see
Documentation/driver-api/io_ordering.rst.
readq_relaxed(), readl_relaxed(), readw_relaxed(), readb_relaxed(),
writeq_relaxed(), writel_relaxed(), writew_relaxed(), writeb_relaxed()
On architectures that require an expensive barrier for serializing against
DMA, these "relaxed" versions of the MMIO accessors only serialize against
each other, but contain a less expensive barrier operation. A device driver
might use these in a particularly performance sensitive fast path, with a
comment that explains why the usage in a specific location is safe without
the extra barriers.
See memory-barriers.txt for a more detailed discussion on the precise ordering
guarantees of the non-relaxed and relaxed versions.
ioread64(), ioread32(), ioread16(), ioread8(),
iowrite64(), iowrite32(), iowrite16(), iowrite8()
These are an alternative to the normal readl()/writel() functions, with almost
identical behavior, but they can also operate on ``__iomem`` tokens returned
for mapping PCI I/O space with pci_iomap() or ioport_map(). On architectures
that require special instructions for I/O port access, this adds a small
overhead for an indirect function call implemented in lib/iomap.c, while on
other architectures, these are simply aliases.
ioread64be(), ioread32be(), ioread16be()
iowrite64be(), iowrite32be(), iowrite16be()
These behave in the same way as the ioread32()/iowrite32() family, but with
reversed byte order, for accessing devices with big-endian MMIO registers.
Device drivers that can operate on either big-endian or little-endian
registers may have to implement a custom wrapper function that picks one or
the other depending on which device was found.
Note: On some architectures, the normal readl()/writel() functions
traditionally assume that devices are the same endianness as the CPU, while
using a hardware byte-reverse on the PCI bus when running a big-endian kernel.
Drivers that use readl()/writel() this way are generally not portable, but
tend to be limited to a particular SoC.
hi_lo_readq(), lo_hi_readq(), hi_lo_readq_relaxed(), lo_hi_readq_relaxed(),
ioread64_lo_hi(), ioread64_hi_lo(), ioread64be_lo_hi(), ioread64be_hi_lo(),
hi_lo_writeq(), lo_hi_writeq(), hi_lo_writeq_relaxed(), lo_hi_writeq_relaxed(),
iowrite64_lo_hi(), iowrite64_hi_lo(), iowrite64be_lo_hi(), iowrite64be_hi_lo()
Some device drivers have 64-bit registers that cannot be accessed atomically
on 32-bit architectures but allow two consecutive 32-bit accesses instead.
Since it depends on the particular device which of the two halves has to be
accessed first, a helper is provided for each combination of 64-bit accessors
with either low/high or high/low word ordering. A device driver must include
either <linux/io-64-nonatomic-lo-hi.h> or <linux/io-64-nonatomic-hi-lo.h> to
get the function definitions along with helpers that redirect the normal
readq()/writeq() to them on architectures that do not provide 64-bit access
natively.
__raw_readq(), __raw_readl(), __raw_readw(), __raw_readb(),
__raw_writeq(), __raw_writel(), __raw_writew(), __raw_writeb()
These are low-level MMIO accessors without barriers or byteorder changes and
architecture specific behavior. Accesses are usually atomic in the sense that
a four-byte __raw_readl() does not get split into individual byte loads, but
multiple consecutive accesses can be combined on the bus. In portable code, it
is only safe to use these to access memory behind a device bus but not MMIO
registers, as there are no ordering guarantees with regard to other MMIO
accesses or even spinlocks. The byte order is generally the same as for normal
memory, so unlike the other functions, these can be used to copy data between
kernel memory and device memory.
inl(), inw(), inb(), outl(), outw(), outb()
PCI I/O port resources traditionally require separate helpers as they are
implemented using special instructions on the x86 architecture. On most other
architectures, these are mapped to readl()/writel() style accessors
internally, usually pointing to a fixed area in virtual memory. Instead of an
``__iomem`` pointer, the address is a 32-bit integer token to identify a port
number. PCI requires I/O port access to be non-posted, meaning that an outb()
must complete before the following code executes, while a normal writeb() may
still be in progress. On architectures that correctly implement this, I/O port
access is therefore ordered against spinlocks. Many non-x86 PCI host bridge
implementations and CPU architectures however fail to implement non-posted I/O
space on PCI, so they can end up being posted on such hardware.
In some architectures, the I/O port number space has a 1:1 mapping to
``__iomem`` pointers, but this is not recommended and device drivers should
not rely on that for portability. Similarly, an I/O port number as described
in a PCI base address register may not correspond to the port number as seen
by a device driver. Portable drivers need to read the port number for the
resource provided by the kernel.
There are no direct 64-bit I/O port accessors, but pci_iomap() in combination
with ioread64/iowrite64 can be used instead.
inl_p(), inw_p(), inb_p(), outl_p(), outw_p(), outb_p()
On ISA devices that require specific timing, the _p versions of the I/O
accessors add a small delay. On architectures that do not have ISA buses,
these are aliases to the normal inb/outb helpers.
readsq, readsl, readsw, readsb
writesq, writesl, writesw, writesb
ioread64_rep, ioread32_rep, ioread16_rep, ioread8_rep
iowrite64_rep, iowrite32_rep, iowrite16_rep, iowrite8_rep
insl, insw, insb, outsl, outsw, outsb
These are helpers that access the same address multiple times, usually to copy
data between kernel memory byte stream and a FIFO buffer. Unlike the normal
MMIO accessors, these do not perform a byteswap on big-endian kernels, so the
first byte in the FIFO register corresponds to the first byte in the memory
buffer regardless of the architecture.
Device memory mapping modes
===========================
Some architectures support multiple modes for mapping device memory.
ioremap_*() variants provide a common abstraction around these
architecture-specific modes, with a shared set of semantics.
ioremap() is the most common mapping type, and is applicable to typical device
memory (e.g. I/O registers). Other modes can offer weaker or stronger
guarantees, if supported by the architecture. From most to least common, they
are as follows:
ioremap()
---------
The default mode, suitable for most memory-mapped devices, e.g. control
registers. Memory mapped using ioremap() has the following characteristics:
* Uncached - CPU-side caches are bypassed, and all reads and writes are handled
directly by the device
* No speculative operations - the CPU may not issue a read or write to this
memory, unless the instruction that does so has been reached in committed
program flow.
* No reordering - The CPU may not reorder accesses to this memory mapping with
respect to each other. On some architectures, this relies on barriers in
readl_relaxed()/writel_relaxed().
* No repetition - The CPU may not issue multiple reads or writes for a single
program instruction.
* No write-combining - Each I/O operation results in one discrete read or write
being issued to the device, and multiple writes are not combined into larger
writes. This may or may not be enforced when using __raw I/O accessors or
pointer dereferences.
* Non-executable - The CPU is not allowed to speculate instruction execution
from this memory (it probably goes without saying, but you're also not
allowed to jump into device memory).
On many platforms and buses (e.g. PCI), writes issued through ioremap()
mappings are posted, which means that the CPU does not wait for the write to
actually reach the target device before retiring the write instruction.
On many platforms, I/O accesses must be aligned with respect to the access
size; failure to do so will result in an exception or unpredictable results.
ioremap_wc()
------------
Maps I/O memory as normal memory with write combining. Unlike ioremap(),
* The CPU may speculatively issue reads from the device that the program
didn't actually execute, and may choose to basically read whatever it wants.
* The CPU may reorder operations as long as the result is consistent from the
program's point of view.
* The CPU may write to the same location multiple times, even when the program
issued a single write.
* The CPU may combine several writes into a single larger write.
This mode is typically used for video framebuffers, where it can increase
performance of writes. It can also be used for other blocks of memory in
devices (e.g. buffers or shared memory), but care must be taken as accesses are
not guaranteed to be ordered with respect to normal ioremap() MMIO register
accesses without explicit barriers.
On a PCI bus, it is usually safe to use ioremap_wc() on MMIO areas marked as
``IORESOURCE_PREFETCH``, but it may not be used on those without the flag.
For on-chip devices, there is no corresponding flag, but a driver can use
ioremap_wc() on a device that is known to be safe.
ioremap_wt()
------------
Maps I/O memory as normal memory with write-through caching. Like ioremap_wc(),
but also,
* The CPU may cache writes issued to and reads from the device, and serve reads
from that cache.
This mode is sometimes used for video framebuffers, where drivers still expect
writes to reach the device in a timely manner (and not be stuck in the CPU
cache), but reads may be served from the cache for efficiency. However, it is
rarely useful these days, as framebuffer drivers usually perform writes only,
for which ioremap_wc() is more efficient (as it doesn't needlessly trash the
cache). Most drivers should not use this.
ioremap_np()
------------
Like ioremap(), but explicitly requests non-posted write semantics. On some
architectures and buses, ioremap() mappings have posted write semantics, which
means that writes can appear to "complete" from the point of view of the
CPU before the written data actually arrives at the target device. Writes are
still ordered with respect to other writes and reads from the same device, but
due to the posted write semantics, this is not the case with respect to other
devices. ioremap_np() explicitly requests non-posted semantics, which means
that the write instruction will not appear to complete until the device has
received (and to some platform-specific extent acknowledged) the written data.
This mapping mode primarily exists to cater for platforms with bus fabrics that
require this particular mapping mode to work correctly. These platforms set the
``IORESOURCE_MEM_NONPOSTED`` flag for a resource that requires ioremap_np()
semantics and portable drivers should use an abstraction that automatically
selects it where appropriate (see the `Higher-level ioremap abstractions`_
section below).
The bare ioremap_np() is only available on some architectures; on others, it
always returns NULL. Drivers should not normally use it, unless they are
platform-specific or they derive benefit from non-posted writes where
supported, and can fall back to ioremap() otherwise. The normal approach to
ensure posted write completion is to do a dummy read after a write as
explained in `Accessing the device`_, which works with ioremap() on all
platforms.
ioremap_np() should never be used for PCI drivers. PCI memory space writes are
always posted, even on architectures that otherwise implement ioremap_np().
Using ioremap_np() for PCI BARs will at best result in posted write semantics,
and at worst result in complete breakage.
Note that non-posted write semantics are orthogonal to CPU-side ordering
guarantees. A CPU may still choose to issue other reads or writes before a
non-posted write instruction retires. See the previous section on MMIO access
functions for details on the CPU side of things.
ioremap_uc()
------------
ioremap_uc() is only meaningful on old x86-32 systems with the PAT extension,
and on ia64 with its slightly unconventional ioremap() behavior, everywhere
elss ioremap_uc() defaults to return NULL.
Portable drivers should avoid the use of ioremap_uc(), use ioremap() instead.
ioremap_cache()
---------------
ioremap_cache() effectively maps I/O memory as normal RAM. CPU write-back
caches can be used, and the CPU is free to treat the device as if it were a
block of RAM. This should never be used for device memory which has side
effects of any kind, or which does not return the data previously written on
read.
It should also not be used for actual RAM, as the returned pointer is an
``__iomem`` token. memremap() can be used for mapping normal RAM that is outside
of the linear kernel memory area to a regular pointer.
Portable drivers should avoid the use of ioremap_cache().
Architecture example
--------------------
Here is how the above modes map to memory attribute settings on the ARM64
architecture:
+------------------------+--------------------------------------------+
| API | Memory region type and cacheability |
+------------------------+--------------------------------------------+
| ioremap_np() | Device-nGnRnE |
+------------------------+--------------------------------------------+
| ioremap() | Device-nGnRE |
+------------------------+--------------------------------------------+
| ioremap_uc() | (not implemented) |
+------------------------+--------------------------------------------+
| ioremap_wc() | Normal-Non Cacheable |
+------------------------+--------------------------------------------+
| ioremap_wt() | (not implemented; fallback to ioremap) |
+------------------------+--------------------------------------------+
| ioremap_cache() | Normal-Write-Back Cacheable |
+------------------------+--------------------------------------------+
Higher-level ioremap abstractions
=================================
Instead of using the above raw ioremap() modes, drivers are encouraged to use
higher-level APIs. These APIs may implement platform-specific logic to
automatically choose an appropriate ioremap mode on any given bus, allowing for
a platform-agnostic driver to work on those platforms without any special
cases. At the time of this writing, the following ioremap() wrappers have such
logic:
devm_ioremap_resource()
Can automatically select ioremap_np() over ioremap() according to platform
requirements, if the ``IORESOURCE_MEM_NONPOSTED`` flag is set on the struct
resource. Uses devres to automatically unmap the resource when the driver
probe() function fails or a device in unbound from its driver.
Documented in Documentation/driver-api/driver-model/devres.rst.
of_address_to_resource()
Automatically sets the ``IORESOURCE_MEM_NONPOSTED`` flag for platforms that
require non-posted writes for certain buses (see the nonposted-mmio and
posted-mmio device tree properties).
of_iomap()
Maps the resource described in a ``reg`` property in the device tree, doing
all required translations. Automatically selects ioremap_np() according to
platform requirements, as above.
pci_ioremap_bar(), pci_ioremap_wc_bar()
Maps the resource described in a PCI base address without having to extract
the physical address first.
pci_iomap(), pci_iomap_wc()
Like pci_ioremap_bar()/pci_ioremap_bar(), but also works on I/O space when
used together with ioread32()/iowrite32() and similar accessors
pcim_iomap()
Like pci_iomap(), but uses devres to automatically unmap the resource when
the driver probe() function fails or a device in unbound from its driver
Documented in Documentation/driver-api/driver-model/devres.rst.
Not using these wrappers may make drivers unusable on certain platforms with
stricter rules for mapping I/O memory.
Generalizing Access to System and I/O Memory
============================================
.. kernel-doc:: include/linux/iosys-map.h
:doc: overview
.. kernel-doc:: include/linux/iosys-map.h
:internal:
Public Functions Provided
=========================
.. kernel-doc:: arch/x86/include/asm/io.h
:internal:
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
Bus-independent device access 소개
1-22.. Copyright 2001 Matthew Wilcox
..
.. This documentation is free software; you can redistribute
.. it and/or modify it under the terms of the GNU General Public
.. License as published by the Free Software Foundation; either
.. version 2 of the License, or (at your option) any later
.. version.Copyright 2001 Matthew Wilcox. 이 documentation은 Free Software Foundation이 공표한 GNU General Public License version 2 또는 선택에 따라 이후 version의 조건으로 재배포하거나 수정할 수 있는 free software입니다.
저자는 Matthew Wilcox와 Alan Cox입니다. Linux는 모든 bus와 device에서 IO를 수행하는 방식을 추상화하는 API를 제공하므로 device driver를 bus type과 독립적으로 작성할 수 있습니다.
Memory-mapped IO address 얻기
23-47가장 널리 지원되는 IO 형태는 memory-mapped IO입니다. CPU address space 일부가 memory access가 아니라 device access로 해석됩니다. 일부 architecture는 device를 fixed address에 두지만 대부분은 PCI bus walk 같은 discovery method를 제공합니다.
이 문서는 physical address를 얻는 방법을 다루지 않고 이미 address가 있다고 가정합니다. physical address type은 `unsigned long`이지만 이 값을 직접 사용해서는 안 됩니다.
아래 accessor function에 전달할 address를 얻으려면 `ioremap()`을 호출합니다. device access에 적합한 address가 반환됩니다. device 사용을 마치면 module exit routine 등에서 `iounmap()`을 호출해 address space를 kernel에 돌려줘야 합니다. 많은 architecture는 `ioremap()` 호출마다 새 address space를 할당하므로 `iounmap()`하지 않으면 고갈될 수 있습니다.
MMIO register access와 ordering
48-84driver가 가장 많이 쓰는 interface는 device의 memory-mapped register를 읽고 쓰는 것입니다. Linux는 8-bit, 16-bit, 32-bit, 64-bit quantity를 지원하며 역사적인 이유로 byte, word, long, quad access라고 부릅니다. read와 write를 모두 지원하지만 현재 prefetch support는 없습니다.
function은 `readb()`, `readw()`, `readl()`, `readq()`, relaxed variant인 `readb_relaxed()`부터 `readq_relaxed()`, 그리고 `writeb()`, `writew()`, `writel()`, `writeq()`입니다.
framebuffer처럼 한 번에 8 byte보다 큰 transfer가 필요한 device에는 `memcpy_toio()`, `memcpy_fromio()`, `memset_io()`를 제공합니다. IO address에 일반 `memset`이나 `memcpy`를 사용하면 data copy order가 보장되지 않으므로 사용하지 마십시오.
기본 read/write function은 ordered로 정의되어 compiler가 I/O sequence를 reorder할 수 없습니다. compiler ordering을 완화해도 되는 경우 `__readb()` 계열을 사용할 수 있지만 주의해야 합니다.
기본 function끼리는 synchronous하고 ordered지만 실제 bus는 asynchronous할 수 있습니다. 특히 PCI bus write는 posted되어 비동기로 진행됩니다. 특정 write가 device에 도달했음을 보장하려면 같은 device를 read해야 합니다. reset 중인 card처럼 flush read가 실패할 수 있으면 응답이 없어도 soft-fail이 보장되는 config space에서 읽어야 합니다.
Posted write flush와 relaxed read
85-118다음 example은 write effect가 보인 뒤 execution을 계속하려고 같은 register를 read하여 device write를 flush합니다.
static inline void
qla1280_disable_intrs(struct scsi_qla_host *ha)
{
struct device_reg *reg;
reg = ha->iobase;
/* disable risc and host interrupts */
WRT_REG_WORD(®->ictrl, 0);
/*
* The following read will ensure that the above write
* has been received by the device before we return from this
* function.
*/
RD_REG_WORD(®->ictrl);
ha->flags.ints_enabled = 0;
}`qla1280_disable_intrs()`는 `WRT_REG_WORD()`로 interrupt를 끈 뒤 같은 `ictrl` register를 `RD_REG_WORD()`로 읽습니다. 이 read가 완료되면 앞선 write가 device에 수신되었음을 보장할 수 있습니다.
PCI ordering rule은 PIO read response가 해당 bus의 outstanding DMA write 뒤에 도착하도록 보장합니다. 어떤 device에서는 `readb()` 결과가 DMA transaction 완료를 알릴 수 있습니다.
다음 `readb()`가 이전 DMA write와 무관하다고 driver가 알 수 있으면 `readb_relaxed()`를 사용할 수 있습니다. 일부 platform만 relaxed semantics를 존중하지만 지원 platform에서는 성능 이점이 큽니다. qla2xxx driver의 `readX_relaxed()` 사용례처럼 DMA completion을 나타내거나 의존하는 소수 access를 제외한 많은 `readX()`를 안전하게 relaxed variant로 바꿀 수 있습니다.
Port Space access
119-148흔히 지원되는 또 다른 IO 형태는 Port Space입니다. normal memory address space와 분리된 address range이며 memory-mapped address보다 느리고 address space도 더 작을 수 있습니다. MMIO와 달리 port space access에는 사전 준비가 필요하지 않습니다.
8-bit, 16-bit, 32-bit access, 즉 byte, word, long access는 `inb()`, `inw()`, `inl()`, `outb()`, `outw()`, `outl()`로 제공합니다.
port access를 늦춰야 하는 device에는 function name 끝에 `_p`를 붙인 variant를 사용합니다. `memcpy`에 해당하는 `ins()`와 `outs()`는 byte, word, long을 지정 port로 복사합니다.
__iomem pointer token
149-165MMIO address의 data type은 `void __iomem *reg` 같은 `__iomem` qualified pointer입니다. 대부분의 architecture에서는 virtual memory address를 가리키는 일반 pointer라 offset하거나 dereference할 수 있지만 portable code에서는 `__iomem` token을 명시적으로 다루는 function 사이에서만 전달해야 합니다. 대표적으로 `ioremap()`과 `readl()`/`writel()`입니다. `sparse` semantic code checker로 올바른 사용을 검증할 수 있습니다.
대부분의 architecture에서 `ioremap()`은 physical MMIO address를 가리키는 uncached virtual address page table entry를 만듭니다. 하지만 일부 architecture는 MMIO 전용 instruction이 필요하며 `__iomem` pointer는 physical address 또는 `readl()`/`writel()`이 해석하는 offsettable cookie만 encode합니다.
Generic accessor와 relaxed accessor
166-190`readq/readl/readw/readb`와 `writeq/writel/writew/writeb`는 가장 generic한 accessor입니다. 다른 MMIO 및 DMA access와 serialization을 제공하고 little-endian PCI device와 on-chip peripheral에 접근하도록 fixed endianness를 적용합니다. portable driver는 일반적으로 모든 `__iomem` access에 이들을 사용해야 합니다.
posted write는 spinlock에 대해 엄격히 ordered되지 않습니다. 자세한 내용은 `Documentation/driver-api/io_ordering.rst`를 참조합니다.
`*_relaxed()` variant는 DMA serialization에 비싼 barrier가 필요한 architecture에서 서로에 대해서만 serialize하고 더 저렴한 barrier를 사용합니다. performance-sensitive fast path에서 extra barrier 없이 안전한 이유를 comment로 설명한 뒤 사용할 수 있습니다. relaxed와 non-relaxed의 정확한 ordering guarantee는 `memory-barriers.txt`를 참조합니다.
ioread/iowrite, endian, 64-bit non-atomic helper
191-230`ioread64()`, `ioread32()`, `ioread16()`, `ioread8()`과 `iowrite64()`, `iowrite32()`, `iowrite16()`, `iowrite8()`은 보통 `readl()`/`writel()`과 거의 같은 alternative입니다. 추가로 `pci_iomap()` 또는 `ioport_map()`으로 mapping한 PCI I/O space의 `__iomem` token에도 동작합니다. 특수 I/O port instruction이 필요한 architecture에서는 `lib/iomap.c`의 indirect function call overhead가 조금 생기고, 다른 architecture에서는 alias입니다.
`ioread64be()`, `ioread32be()`, `ioread16be()`와 `iowrite64be()`, `iowrite32be()`, `iowrite16be()`는 byte order를 뒤집어 big-endian MMIO register에 접근합니다. big-endian과 little-endian register를 모두 지원하는 driver는 발견한 device에 따라 family를 고르는 custom wrapper가 필요할 수 있습니다.
일부 architecture에서 일반 `readl()`/`writel()`은 device endianness가 CPU와 같다고 가정하고 big-endian kernel의 PCI bus에서 hardware byte-reverse를 사용해 온 전통이 있습니다. 이 방식의 driver는 일반적으로 portable하지 않고 특정 SoC에 한정됩니다.
32-bit architecture에서 atomically access할 수 없는 64-bit register가 연속된 32-bit access 두 번을 허용할 수 있습니다. device마다 어느 half를 먼저 access할지가 다르므로 low/high 또는 high/low 순서와 read/write 조합별 helper를 제공합니다. driver는 `<linux/io-64-nonatomic-lo-hi.h>` 또는 `<linux/io-64-nonatomic-hi-lo.h>`를 include해야 하며, native 64-bit access가 없는 architecture에서는 normal `readq()`/`writeq()`도 이 helper로 redirect됩니다.
Raw MMIO, I/O port, repeated access
231-286`__raw_read*()`와 `__raw_write*()`는 barrier나 byteorder change 없이 architecture-specific behavior를 노출하는 low-level MMIO accessor입니다. 개별 access는 보통 atomic하지만 연속 access가 bus에서 합쳐질 수 있습니다. 다른 MMIO나 spinlock에 대한 ordering guarantee가 없으므로 portable code에서는 MMIO register가 아니라 device bus 뒤의 memory에만 안전합니다. byte order는 normal memory와 같아 kernel memory와 device memory 사이 data copy에 사용할 수 있습니다.
`inl/inw/inb`와 `outl/outw/outb`는 x86의 special instruction으로 구현되는 PCI I/O port resource용 helper입니다. 다른 architecture에서는 fixed virtual memory area를 가리키는 `readl()`/`writel()` style accessor로 mapping되는 경우가 많습니다. address는 `__iomem` pointer가 아니라 port number를 식별하는 32-bit integer token입니다.
PCI I/O port access는 non-posted여야 하므로 `outb()`는 다음 code가 실행되기 전에 완료되어야 하지만 normal `writeb()`는 계속 진행 중일 수 있습니다. 올바른 구현에서는 spinlock에 대해 ordered되지만 많은 non-x86 host bridge와 CPU는 PCI non-posted I/O space를 구현하지 못해 posted가 될 수 있습니다.
일부 architecture의 I/O port number space는 `__iomem` pointer와 1:1 mapping되지만 portable driver는 이에 의존하면 안 됩니다. PCI BAR의 I/O port number도 driver가 보는 번호와 다를 수 있으므로 kernel이 제공한 resource에서 읽어야 합니다. direct 64-bit I/O port accessor는 없지만 `pci_iomap()`과 `ioread64/iowrite64`를 조합할 수 있습니다.
ISA timing이 필요한 device에서는 `_p` variant가 작은 delay를 추가합니다. ISA bus가 없는 architecture에서는 normal `inb/outb` alias입니다. `reads*`, `writes*`, `ioread*_rep`, `iowrite*_rep`, `ins*`, `outs*`는 같은 address를 반복 access해 kernel byte stream과 FIFO buffer 사이 data를 복사합니다. big-endian kernel에서도 byteswap하지 않아 FIFO 첫 byte가 architecture와 무관하게 memory buffer 첫 byte에 대응합니다.
ordering, address token, endian 처리와 대표 용도를 기준으로 주요 accessor family를 정리했습니다.
Device memory mapping mode와 ioremap()
287-329일부 architecture는 device memory mapping mode를 여러 개 지원합니다. `ioremap_*()` variant는 architecture-specific mode를 공통 semantics로 추상화합니다. 가장 흔한 `ioremap()`은 control register 같은 일반 memory-mapped device에 적합한 default입니다.
- Uncached: CPU-side cache를 우회하고 모든 read/write를 device가 직접 처리합니다.
- No speculative operations: committed program flow에서 instruction에 도달하기 전에는 CPU가 read/write를 발행할 수 없습니다.
- No reordering: CPU는 이 mapping에 대한 access끼리 reorder할 수 없습니다. 일부 architecture는 `readl_relaxed()`/`writel_relaxed()` barrier에 의존합니다.
- No repetition: 한 program instruction에 여러 read/write를 발행할 수 없습니다.
- No write-combining: 각 I/O operation은 discrete access 하나가 되며 여러 write를 큰 write로 합치지 않습니다. `__raw` accessor나 pointer dereference에서는 강제되지 않을 수 있습니다.
- Non-executable: CPU는 이 memory에서 instruction execution을 speculate할 수 없고 device memory로 jump해서도 안 됩니다.
PCI 같은 많은 platform과 bus에서 `ioremap()` write는 posted되어 CPU가 target device 도착을 기다리지 않고 instruction을 retire합니다. 또한 많은 platform에서 I/O access는 access size에 맞게 align되어야 하며 그렇지 않으면 exception 또는 unpredictable result가 발생합니다.
ioremap_wc() write-combining mode
330-353`ioremap_wc()`는 I/O memory를 write-combining normal memory로 mapping합니다. `ioremap()`과 달리 CPU가 program이 실행하지 않은 speculative read를 할 수 있고, program 관점의 결과가 같다면 operation을 reorder할 수 있으며, 같은 location에 여러 번 write하거나 여러 write를 하나의 큰 write로 합칠 수 있습니다.
주 용도는 video framebuffer write 성능 향상입니다. device buffer나 shared memory에도 사용할 수 있지만 explicit barrier 없이는 normal `ioremap()` MMIO register access와 ordered된다고 보장되지 않습니다.
PCI bus에서는 보통 `IORESOURCE_PREFETCH`로 표시된 MMIO area에 안전하며 flag가 없는 area에는 사용할 수 없습니다. on-chip device에는 대응 flag가 없지만 driver가 안전함을 아는 device에는 사용할 수 있습니다.
ioremap_wt() write-through mode
354-369`ioremap_wt()`는 I/O memory를 write-through caching normal memory로 mapping합니다. `ioremap_wc()`처럼 동작하면서 CPU가 device write와 read를 cache하고 cache에서 read를 service할 수도 있습니다.
과거에는 write가 적시에 device에 도달하면서 read는 cache로 효율화하려는 video framebuffer에 사용했습니다. 현재 framebuffer driver는 대개 write만 수행하므로 cache를 불필요하게 오염하지 않는 `ioremap_wc()`가 더 효율적입니다. 대부분의 driver는 이 mode를 사용하지 않아야 합니다.
ioremap_np() non-posted mode
370-407`ioremap_np()`는 `ioremap()`과 비슷하지만 non-posted write semantics를 명시적으로 요청합니다. posted mapping에서는 CPU 관점에서 write가 완료된 뒤에도 data가 target device에 아직 도착하지 않을 수 있습니다. 같은 device의 read/write끼리는 ordered되지만 다른 device에 대해서는 그렇지 않습니다.
non-posted semantics에서는 device가 data를 수신하고 platform-specific 범위에서 acknowledge하기 전까지 write instruction이 완료된 것처럼 보이지 않습니다. 이 mode는 특정 mapping이 필요한 bus fabric platform을 위해 존재합니다.
그런 platform은 `ioremap_np()`가 필요한 resource에 `IORESOURCE_MEM_NONPOSTED`를 설정합니다. portable driver는 아래 higher-level abstraction을 사용해 적절한 mode를 자동 선택해야 합니다.
bare `ioremap_np()`는 일부 architecture에서만 제공되고 나머지에서는 항상 `NULL`입니다. platform-specific driver 또는 지원될 때 non-posted write 이점을 얻고 아니면 `ioremap()`으로 fallback할 수 있는 경우가 아니면 직접 사용하지 않아야 합니다. 모든 platform에서 posted write 완료를 보장하는 일반 방법은 write 뒤 dummy read입니다.
PCI memory space write는 항상 posted이므로 PCI driver에서 `ioremap_np()`를 절대 사용하면 안 됩니다. PCI BAR에 쓰면 좋게 끝나도 posted semantics이고 나쁘면 완전히 동작하지 않습니다. 또한 non-posted semantics와 CPU-side ordering guarantee는 서로 독립이므로 CPU는 non-posted write가 retire되기 전에 다른 read/write를 발행할 수 있습니다.
ioremap_uc()와 ioremap_cache()
408-432`ioremap_uc()`는 PAT extension이 있는 오래된 x86-32 system과 특이한 `ioremap()` behavior를 가진 ia64에서만 의미가 있으며 다른 곳에서는 기본적으로 `NULL`을 반환합니다. portable driver는 피하고 `ioremap()`을 사용해야 합니다.
`ioremap_cache()`는 I/O memory를 사실상 normal RAM으로 mapping합니다. CPU write-back cache를 사용할 수 있고 CPU가 device를 RAM block처럼 취급할 수 있습니다. side effect가 있거나 read할 때 이전 write data를 반환하지 않는 device memory에는 절대 사용하면 안 됩니다.
반환 pointer가 `__iomem` token이므로 actual RAM에도 사용하면 안 됩니다. linear kernel memory area 밖의 normal RAM은 `memremap()`으로 regular pointer에 mapping할 수 있습니다. portable driver는 `ioremap_cache()`를 피해야 합니다.
각 ioremap variant의 cache, posting, 주요 용도와 portable 사용 제약을 요약했습니다.
ARM64 memory attribute example
433-454ARM64 architecture에서 위 mode는 다음 memory attribute setting으로 mapping됩니다.
+------------------------+--------------------------------------------+
| API | Memory region type and cacheability |
+------------------------+--------------------------------------------+
| ioremap_np() | Device-nGnRnE |
+------------------------+--------------------------------------------+
| ioremap() | Device-nGnRE |
+------------------------+--------------------------------------------+
| ioremap_uc() | (not implemented) |
+------------------------+--------------------------------------------+
| ioremap_wc() | Normal-Non Cacheable |
+------------------------+--------------------------------------------+
| ioremap_wt() | (not implemented; fallback to ioremap) |
+------------------------+--------------------------------------------+
| ioremap_cache() | Normal-Write-Back Cacheable |
+------------------------+--------------------------------------------+원문 ASCII table을 동일한 API와 memory region type으로 구조화했습니다.
Higher-level ioremap abstraction
455-505raw `ioremap()` mode 대신 higher-level API 사용을 권장합니다. 이 API는 bus별 platform-specific logic으로 적절한 mapping mode를 자동 선택하므로 platform-agnostic driver가 special case 없이 동작할 수 있습니다.
- `devm_ioremap_resource()`는 `struct resource`에 `IORESOURCE_MEM_NONPOSTED`가 있으면 `ioremap()` 대신 `ioremap_np()`를 자동 선택할 수 있습니다. devres로 probe 실패 또는 driver unbind 때 resource를 자동 unmap합니다. `Documentation/driver-api/driver-model/devres.rst`에 문서화되어 있습니다.
- `of_address_to_resource()`는 특정 bus에 non-posted write가 필요한 platform에서 `IORESOURCE_MEM_NONPOSTED`를 자동 설정합니다. `nonposted-mmio`와 `posted-mmio` device tree property를 참조합니다.
- `of_iomap()`은 device tree `reg` property의 resource를 필요한 translation과 함께 mapping하고 platform 요구에 따라 `ioremap_np()`를 자동 선택합니다.
- `pci_ioremap_bar()`와 `pci_ioremap_wc_bar()`는 physical address를 먼저 추출하지 않고 PCI BAR resource를 mapping합니다.
- `pci_iomap()`과 `pci_iomap_wc()`는 PCI BAR mapping과 비슷하지만 `ioread32()`/`iowrite32()` 계열과 함께 I/O space에도 동작합니다.
- `pcim_iomap()`은 `pci_iomap()`과 비슷하며 devres로 probe 실패 또는 unbind 때 자동 unmap합니다. devres 문서를 참조합니다.
platform logic, resource 종류와 lifecycle 관리 기준으로 wrapper를 정리했습니다.
이 wrapper를 사용하지 않으면 I/O memory mapping rule이 엄격한 platform에서 driver가 동작하지 않을 수 있습니다.
System memory와 I/O memory access 일반화
506-519`include/linux/iosys-map.h`의 kernel-doc는 system memory와 I/O memory를 공통으로 다루는 `iosys-map` overview와 internal API를 제공합니다.
.. kernel-doc:: include/linux/iosys-map.h
:doc: overview
.. kernel-doc:: include/linux/iosys-map.h
:internal:공개 function section은 `arch/x86/include/asm/io.h`의 internal kernel-doc를 포함합니다.
.. kernel-doc:: arch/x86/include/asm/io.h
:internal:
요약과 해설
device-io.rst:1-519portable driver는 physical address를 직접 dereference하지 않고 `ioremap()`으로 `__iomem` token을 얻어 ordered accessor로 접근해야 합니다. posted write flush, relaxed DMA barrier, endian 및 64-bit split access, raw/port/FIFO helper의 차이를 이해해야 하며 mapping mode의 cache·posting semantics에 맞는 wrapper를 선택해야 합니다. 일반적으로 `devm_ioremap_resource()`, OF, PCI wrapper가 platform별 non-posted requirement와 lifecycle을 안전하게 처리합니다.