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Linux 6.18.37 · Devicetree Bindings / USB

Rockchip RK3399 DWC3 Controller

RK3399 DWC3 wrapper의 여섯 clock, reset과 child quirk를 설명합니다.

Source pathDocumentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

요약과 해설

rockchip,rk3399-dwc3.yaml:1-115

RK3399 DWC3 wrapper의 여섯 clock, reset과 child quirk를 설명합니다. 접을 수 있는 영어 원문 전체와 한국어 전문 번역을 함께 제공하며, compatible, register, interrupt, clock, reset, PHY, quirk, source path와 원문 줄 좌표를 원형대로 보존합니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
8
9 maintainers:
10 - Heiko Stuebner <[email protected]>
11
12 properties:
13 compatible:
14 const: rockchip,rk3399-dwc3
15
16 '#address-cells':
17 const: 2
18
19 '#size-cells':
20 const: 2
21
22 ranges: true
23
24 clocks:
25 items:
26 - description:
27 Controller reference clock, must to be 24 MHz
28 - description:
29 Controller suspend clock, must to be 24 MHz or 32 KHz
30 - description:
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
33 - description:
34 USB3 aclk peri
35 - description:
36 USB3 aclk
37 - description:
38 Controller grf clock
39
40 clock-names:
41 items:
42 - const: ref_clk
43 - const: suspend_clk
44 - const: bus_clk
45 - const: aclk_usb3_rksoc_axi_perf
46 - const: aclk_usb3
47 - const: grf_clk
48
49 resets:
50 maxItems: 1
51
52 reset-names:
53 const: usb3-otg
54
55 patternProperties:
56 '^usb@':
57 $ref: snps,dwc3.yaml#
58
59 additionalProperties: false
60
61 required:
62 - compatible
63 - '#address-cells'
64 - '#size-cells'
65 - ranges
66 - clocks
67 - clock-names
68 - resets
69 - reset-names
70
71 examples:
72 - |
73 #include <dt-bindings/clock/rk3399-cru.h>
74 #include <dt-bindings/power/rk3399-power.h>
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
76
77 bus {
78 #address-cells = <2>;
79 #size-cells = <2>;
80
81 usb {
82 compatible = "rockchip,rk3399-dwc3";
83 #address-cells = <2>;
84 #size-cells = <2>;
85 ranges;
86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
89 clock-names = "ref_clk", "suspend_clk",
90 "bus_clk", "aclk_usb3_rksoc_axi_perf",
91 "aclk_usb3", "grf_clk";
92 resets = <&cru SRST_A_USB3_OTG0>;
93 reset-names = "usb3-otg";
94
95 usb@fe800000 {
96 compatible = "snps,dwc3";
97 reg = <0x0 0xfe800000 0x0 0x100000>;
98 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
100 <&cru SCLK_USB3OTG0_SUSPEND>;
101 clock-names = "ref", "bus_early", "suspend";
102 dr_mode = "otg";
103 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
104 phy-names = "usb2-phy", "usb3-phy";
105 phy_type = "utmi_wide";
106 snps,dis_enblslpm_quirk;
107 snps,dis-u2-freeclk-exists-quirk;
108 snps,dis_u2_susphy_quirk;
109 snps,dis-del-phy-power-chg-quirk;
110 snps,dis-tx-ipgap-linecheck-quirk;
111 power-domains = <&power RK3399_PD_USB3>;
112 };
113 };
114 };
115 ...
116

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

RK3399 DWC3 wrapper

1-11

GPL-2.0으로 배포되는 이 스키마는 Rockchip RK3399 SuperSpeed DWC3 USB SoC controller wrapper를 정의합니다. 관리자는 Heiko Stuebner입니다.

bus cell, 여섯 clock과 reset

12-54

compatible은 `rockchip,rk3399-dwc3`이고 child 주소와 크기는 각각 2-cell이며 `ranges`를 사용합니다. clock 여섯 개는 24 MHz reference, 24 MHz 또는 32 KHz suspend, SS 62.5 MHz 이상·HS 30 MHz 이상 bus, USB3 ACLK peripheral, USB3 ACLK, GRF clock 순서입니다.

clock 이름은 `ref_clk`, `suspend_clk`, `bus_clk`, `aclk_usb3_rksoc_axi_perf`, `aclk_usb3`, `grf_clk`입니다. reset은 하나이고 이름은 `usb3-otg`입니다.

properties:
  compatible:
    const: rockchip,rk3399-dwc3

  '#address-cells':
    const: 2

  '#size-cells':
    const: 2

  ranges: true

  clocks:
    items:
      - description:
          Controller reference clock, must to be 24 MHz
      - description:
          Controller suspend clock, must to be 24 MHz or 32 KHz
      - description:
          Master/Core clock, must to be >= 62.5 MHz for SS
          operation and >= 30MHz for HS operation
      - description:
          USB3 aclk peri
      - description:
          USB3 aclk
      - description:
          Controller grf clock

  clock-names:
    items:
      - const: ref_clk
      - const: suspend_clk
      - const: bus_clk
      - const: aclk_usb3_rksoc_axi_perf
      - const: aclk_usb3
      - const: grf_clk

  resets:
    maxItems: 1

  reset-names:
    const: usb3-otg

DWC3 child와 필수 속성

55-70

`usb@...` child는 `snps,dwc3.yaml`을 따릅니다. wrapper 필수 속성은 `compatible`, address/size cell, `ranges`, `clocks`, `clock-names`, `resets`, `reset-names`이며 추가 속성은 허용하지 않습니다.

patternProperties:
  '^usb@':
    $ref: snps,dwc3.yaml#

additionalProperties: false

required:
  - compatible
  - '#address-cells'
  - '#size-cells'
  - ranges
  - clocks
  - clock-names
  - resets
  - reset-names

RK3399 wrapper와 DWC3 child 예제

71-115

예제 wrapper는 여섯 clock과 `SRST_A_USB3_OTG0` reset을 연결합니다. child `usb@fe800000`은 Synopsys DWC3, GIC SPI 105, `ref`·`bus_early`·`suspend` clock, USB2·USB3 PHY와 `utmi_wide`를 사용합니다.

child는 enable sleep, U2 free clock, U2 suspend PHY, delayed PHY power change, TX IP gap line check 관련 다섯 quirk를 비활성화하고 RK3399 USB3 power domain을 연결합니다.

examples:
  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/power/rk3399-power.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        usb {
            compatible = "rockchip,rk3399-dwc3";
            #address-cells = <2>;
            #size-cells = <2>;
            ranges;
            clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
                     <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
                     <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
            clock-names = "ref_clk", "suspend_clk",
                          "bus_clk", "aclk_usb3_rksoc_axi_perf",
                          "aclk_usb3", "grf_clk";
            resets = <&cru SRST_A_USB3_OTG0>;
            reset-names = "usb3-otg";

            usb@fe800000 {
                compatible = "snps,dwc3";
                reg = <0x0 0xfe800000 0x0 0x100000>;
                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
                         <&cru SCLK_USB3OTG0_SUSPEND>;
                clock-names = "ref", "bus_early", "suspend";
                dr_mode = "otg";
                phys = <&u2phy0_otg>, <&tcphy0_usb3>;
                phy-names = "usb2-phy", "usb3-phy";
                phy_type = "utmi_wide";
                snps,dis_enblslpm_quirk;
                snps,dis-u2-freeclk-exists-quirk;
                snps,dis_u2_susphy_quirk;
                snps,dis-del-phy-power-chg-quirk;
                snps,dis-tx-ipgap-linecheck-quirk;
                power-domains = <&power RK3399_PD_USB3>;
            };
        };
    };
...