ARM Architected Timer

ARM per-core architected timer

GPL-2.0 라이선스의 이 스키마는 ARM architected timer를 정의합니다. Per-core timer는 CPU별 timer를 제공하고 GIC에 연결되어 PPI로 interrupt를 전달합니다. Memory-mapped architected timer는 최대 8개 frame의 physical timer와 선택적인 virtual timer를 제공하고 SPI로 interrupt를 전달합니다. Maintainer는 Marc Zyngier와 Mark Rutland입니다.

Compatible과 interrupt 순서

Compatible 조합은 `arm,cortex-a15-timer`와 `arm,armv7-timer`, 단독 `arm,armv7-timer` 또는 `arm,armv8-timer`, 그리고 `arm,armv8-timer` 뒤에 `arm,armv7-timer` fallback을 둔 형태입니다. `interrupts` 순서는 secure timer, non-secure timer, virtual timer, hypervisor timer, hypervisor virtual timer IRQ입니다.

`interrupt-names`는 secure IRQ가 없으면 `phys`, `virt`, `hyp-phys`, `hyp-virt` 순서이고 최소 2개입니다. Secure IRQ가 있으면 앞에 `sec-phys`를 더한 순서이며 최소 3개입니다.

properties:
  compatible:
    oneOf:
      - items:
          - const: arm,cortex-a15-timer
          - const: arm,armv7-timer
      - items:
          - enum:
              - arm,armv7-timer
              - arm,armv8-timer
      - items:
          - const: arm,armv8-timer
          - const: arm,armv7-timer

  interrupts:
    minItems: 1
    items:
      - description: secure timer irq
      - description: non-secure timer irq
      - description: virtual timer irq
      - description: hypervisor timer irq
      - description: hypervisor virtual timer irq

  interrupt-names:
    oneOf:
      - minItems: 2
        items:
          - const: phys
          - const: virt
          - const: hyp-phys
          - const: hyp-virt
      - minItems: 3
        items:
          - const: sec-phys
          - const: phys
          - const: virt
          - const: hyp-phys
          - const: hyp-virt

Counter 주파수와 세 erratum

`clock-frequency`는 firmware가 모든 CPU의 `CNTFRQ`를 동일한 올바른 값으로 구성하지 못한 경우에만 main counter 주파수를 Hz로 지정하는 우회 속성이며 사용을 강하게 권장하지 않습니다. `always-on`은 timer가 context를 잃지 않는 always-on power domain에 있음을 뜻합니다.

`allwinner,erratum-unknown1`은 특정 counter value 판독이 불안정하고 implicit counter read 때문에 `tval` write도 영향을 받는 문제입니다. `fsl,erratum-a008585`는 연속한 back-to-back read에서 같은 값이 반환되어야 판독을 신뢰할 수 있는 QorIQ A-008585를 나타냅니다. `hisilicon,erratum-161010101`은 일부 판독이 올바른 값보다 32 큰 값을 반환할 수 있고 `tval` register write에도 영향을 주는 문제입니다.

clock-frequency:
  description: The frequency of the main counter, in Hz. Should be present
    only where necessary to work around broken firmware which does not configure
    CNTFRQ on all CPUs to a uniform correct value. Use of this property is
    strongly discouraged; fix your firmware unless absolutely impossible.

always-on:
  type: boolean
  description: If present, the timer is powered through an always-on power
    domain, therefore it never loses context.

allwinner,erratum-unknown1:
  type: boolean
  description: Indicates the presence of an erratum found in Allwinner SoCs,
    where reading certain values from the counter is unreliable. This also
    affects writes to the tval register, due to the implicit counter read.

fsl,erratum-a008585:
  type: boolean
  description: Indicates the presence of QorIQ erratum A-008585, which says
    that reading the counter is unreliable unless the same value is returned
    by back-to-back reads. This also affects writes to the tval register, due
    to the implicit counter read.

hisilicon,erratum-161010101:
  type: boolean
  description: Indicates the presence of Hisilicon erratum 161010101, which
    says that reading the counters is unreliable in some cases, and reads may
    return a value 32 beyond the correct value. This also affects writes to
    the tval registers, due to the implicit counter read.

Firmware 초기화와 suspend 조건

`arm,cpu-registers-not-fw-configured`는 firmware가 architecturally-defined reset value를 가진 generic timer CPU register를 초기화하지 않았음을 나타내며 ARMv7 reset value를 따르는 32-bit system에서만 지원됩니다. `arm,no-tick-in-suspend`는 low-power system suspend 중 main counter가 멈추는 SoC를 표시하고 always-on 요구와 맞지 않는 동작임을 알립니다. `compatible`은 필수이며 `interrupts` 또는 `interrupts-extended` 중 하나가 반드시 있어야 합니다.

  arm,cpu-registers-not-fw-configured:
    type: boolean
    description: Firmware does not initialize any of the generic timer CPU
      registers, which contain their architecturally-defined reset values. Only
      supported for 32-bit systems which follow the ARMv7 architected reset
      values.

  arm,no-tick-in-suspend:
    type: boolean
    description: The main counter does not tick when the system is in
      low-power system suspend on some SoCs. This behavior does not match the
      Architecture Reference Manual's specification that the system counter "must
      be implemented in an always-on power domain."

required:
  - compatible

additionalProperties: false

oneOf:
  - required:
      - interrupts
  - required:
      - interrupts-extended

Cortex-A15 네 PPI 예제

예제는 `arm,cortex-a15-timer`와 `arm,armv7-timer` compatible을 사용합니다. Secure, non-secure, virtual, hypervisor timer에 해당하는 PPI 13, 14, 11, 10을 지정하고 main counter frequency를 100000000Hz로 설정합니다.

  - |
    timer {
      compatible = "arm,cortex-a15-timer",
             "arm,armv7-timer";
      interrupts = <1 13 0xf08>,
             <1 14 0xf08>,
             <1 11 0xf08>,
             <1 10 0xf08>;
      clock-frequency = <100000000>;
    };

...