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Linux 6.18.37 · Devicetree Bindings

Marvell Armada 37xx Pin and GPIO Controller

Armada 37xx north/south bridge pinctrl·GPIO·syscon binding입니다.

Source pathDocumentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

요약과 해설

marvell,armada-37xx-pinctrl.txt:1-195

Bridge별 30개 group, GPIO interrupt, crystal clock와 RGMII 예제를 설명합니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 * Marvell Armada 37xx SoC pin and gpio controller
2
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
4 south bridge and the other for the north bridge.
5
6 Inside this set of register the gpio latch allows exposing some
7 configuration of the SoC and especially the clock frequency of the
8 xtal. Hence, this node is a represent as syscon allowing sharing the
9 register between multiple hardware block.
10
11 GPIO and pin controller:
12 ------------------------
13
14 Main node:
15
16 Refer to pinctrl-bindings.txt in this directory for details of the
17 common pinctrl bindings used by client devices, including the meaning
18 of the phrase "pin configuration node".
19
20 Required properties for pinctrl driver:
21
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
23 for the south bridge
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
25 for the north bridge
26 - reg: The first set of register are for pinctrl/gpio and the second
27 set for the interrupt controller
28 - interrupts: list of the interrupt use by the gpio
29
30 Available groups and functions for the North bridge:
31
32 group: jtag
33 - pins 20-24
34 - functions jtag, gpio
35
36 group sdio0
37 - pins 8-10
38 - functions sdio, gpio
39
40 group emmc_nb
41 - pins 27-35
42 - functions emmc, gpio
43
44 group pwm0
45 - pin 11 (GPIO1-11)
46 - functions pwm, led, gpio
47
48 group pwm1
49 - pin 12
50 - functions pwm, led, gpio
51
52 group pwm2
53 - pin 13
54 - functions pwm, led, gpio
55
56 group pwm3
57 - pin 14
58 - functions pwm, led, gpio
59
60 group pmic1
61 - pin 7
62 - functions pmic, gpio
63
64 group pmic0
65 - pin 6
66 - functions pmic, gpio
67
68 group i2c2
69 - pins 2-3
70 - functions i2c, gpio
71
72 group i2c1
73 - pins 0-1
74 - functions i2c, gpio
75
76 group spi_cs1
77 - pin 17
78 - functions spi, gpio
79
80 group spi_cs2
81 - pin 18
82 - functions spi, gpio
83
84 group spi_cs3
85 - pin 19
86 - functions spi, gpio
87
88 group onewire
89 - pin 4
90 - functions onewire, gpio
91
92 group uart1
93 - pins 25-26
94 - functions uart, gpio
95
96 group spi_quad
97 - pins 15-16
98 - functions spi, gpio
99
100 group uart2
101 - pins 9-10 and 18-19
102 - functions uart, gpio
103
104 Available groups and functions for the South bridge:
105
106 group usb32_drvvbus0
107 - pin 36
108 - functions drvbus, gpio
109
110 group usb2_drvvbus1
111 - pin 37
112 - functions drvbus, gpio
113
114 group sdio_sb
115 - pins 60-65
116 - functions sdio, gpio
117
118 group rgmii
119 - pins 42-53
120 - functions mii, gpio
121
122 group pcie1
123 - pins 39
124 - functions pcie, gpio
125
126 group pcie1_clkreq
127 - pins 40
128 - functions pcie, gpio
129
130 group pcie1_wakeup
131 - pins 41
132 - functions pcie, gpio
133
134 group smi
135 - pins 54-55
136 - functions smi, gpio
137
138 group ptp
139 - pins 56
140 - functions ptp, gpio
141
142 group ptp_clk
143 - pin 57
144 - functions ptp, mii
145
146 group ptp_trig
147 - pin 58
148 - functions ptp, mii
149
150 group mii_col
151 - pin 59
152 - functions mii, mii_err
153
154 GPIO subnode:
155
156 Please refer to gpio.txt in this directory for details of gpio-ranges property
157 and the common GPIO bindings used by client devices.
158
159 Required properties for gpio driver under the gpio subnode:
160 - interrupts: List of interrupt specifier for the controllers interrupt.
161 - gpio-controller: Marks the device node as a gpio controller.
162 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
163 second cell specifies GPIO flags, as defined in
164 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
165 GPIO_ACTIVE_LOW flags are supported.
166 - gpio-ranges: Range of pins managed by the GPIO controller.
167
168 Xtal Clock bindings for Marvell Armada 37xx SoCs
169 ------------------------------------------------
170
171 see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
172
173
174 Example:
175 pinctrl_sb: pinctrl-sb@18800 {
176 compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
177 reg = <0x18800 0x100>, <0x18C00 0x20>;
178 gpio {
179 #gpio-cells = <2>;
180 gpio-ranges = <&pinctrl_sb 0 0 29>;
181 gpio-controller;
182 interrupts =
183 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
188 };
189
190 rgmii_pins: mii-pins {
191 groups = "rgmii";
192 function = "mii";
193 };
194
195 };
196

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

Armada 37xx pin·GPIO controller

1-10

각 Armada 37xx SoC에는 south bridge용과 north bridge용 pin/GPIO controller가 하나씩 있습니다.

이 register 집합 안의 GPIO latch는 crystal oscillator의 clock frequency를 비롯한 일부 SoC configuration을 외부에 제공합니다. 따라서 이 노드는 여러 hardware block이 register를 공유할 수 있도록 `syscon`으로도 표현합니다.

Armada 37xx main node 속성

11-29

Client device의 공통 pinctrl binding과 `pin configuration node`의 의미는 `pinctrl-bindings.txt`를 참조합니다.

South bridge의 `compatible` 목록은 `marvell,armada3710-sb-pinctrl`, `syscon`, `simple-mfd`이고 north bridge는 `marvell,armada3710-nb-pinctrl`, `syscon`, `simple-mfd`입니다.

`reg`의 첫 register 집합은 pinctrl/GPIO용이고 둘째 집합은 interrupt controller용입니다. `interrupts`에는 GPIO가 사용하는 interrupt 목록을 지정합니다.

North bridge group과 function

30-103

North bridge의 JTAG, SDIO, eMMC, PWM, PMIC, I2C, SPI chip-select, 1-Wire, UART group과 해당 pin/function 전체입니다.

BridgeGroupPinsFunctions
North bridgejtag20-24jtag, gpio
North bridgesdio08-10sdio, gpio
North bridgeemmc_nb27-35emmc, gpio
North bridgepwm011 (GPIO1-11)pwm, led, gpio
North bridgepwm112pwm, led, gpio
North bridgepwm213pwm, led, gpio
North bridgepwm314pwm, led, gpio
North bridgepmic17pmic, gpio
North bridgepmic06pmic, gpio
North bridgei2c22-3i2c, gpio
North bridgei2c10-1i2c, gpio
North bridgespi_cs117spi, gpio
North bridgespi_cs218spi, gpio
North bridgespi_cs319spi, gpio
North bridgeonewire4onewire, gpio
North bridgeuart125-26uart, gpio
North bridgespi_quad15-16spi, gpio
North bridgeuart29-10 and 18-19uart, gpio

South bridge group과 function

104-153

South bridge의 USB VBUS drive, SDIO, RGMII, PCIe, SMI, PTP, MII collision group과 pin/function 전체입니다.

BridgeGroupPinsFunctions
South bridgeusb32_drvvbus036drvbus, gpio
South bridgeusb2_drvvbus137drvbus, gpio
South bridgesdio_sb60-65sdio, gpio
South bridgergmii42-53mii, gpio
South bridgepcie139pcie, gpio
South bridgepcie1_clkreq40pcie, gpio
South bridgepcie1_wakeup41pcie, gpio
South bridgesmi54-55smi, gpio
South bridgeptp56ptp, gpio
South bridgeptp_clk57ptp, mii
South bridgeptp_trig58ptp, mii
South bridgemii_col59mii, mii_err

Armada 37xx GPIO 하위 노드

154-167

`gpio-ranges`와 공통 GPIO binding은 같은 directory의 `gpio.txt`를 참조합니다.

GPIO 하위 노드의 필수 `interrupts`는 controller interrupt specifier 목록입니다. `gpio-controller`는 GPIO controller임을 표시하고 `#gpio-cells`는 2여야 합니다.

첫 GPIO cell은 GPIO 번호, 둘째 cell은 `dt-bindings/gpio/gpio.h`의 flag입니다. `GPIO_ACTIVE_HIGH`와 `GPIO_ACTIVE_LOW`만 지원합니다. `gpio-ranges`에는 controller가 관리하는 pin 범위를 지정합니다.

Armada 37xx crystal clock binding

168-173

Armada 37xx SoC의 crystal clock binding은 `Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt`를 참조합니다.

Armada 37xx south bridge 예제

174-195

예제는 south bridge pinctrl/syscon 노드에 GPIO 하위 노드와 interrupt 다섯 개를 정의하고, `rgmii` group을 `mii` function으로 선택합니다.

pinctrl_sb: pinctrl-sb@18800 {
        compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
        reg = <0x18800 0x100>, <0x18C00 0x20>;
        gpio {
                #gpio-cells = <2>;
                gpio-ranges = <&pinctrl_sb 0 0 29>;
                gpio-controller;
                interrupts =
                <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
                <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
                <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
                <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
                <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
        };

        rgmii_pins: mii-pins {
                groups = "rgmii";
                function = "mii";
        };

};