요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
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.. SPDX-License-Identifier: GPL-2.0
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=======================================
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IRQ chip model (hierarchy) of LoongArch
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=======================================
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Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
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with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
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Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
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I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
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PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
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in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
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CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
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controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
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in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
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and there are two models of hierarchy (legacy model and extended model).
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Legacy IRQ model
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================
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
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to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
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interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
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to LIOINTC, and then CPUINTC::
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+-----+ +---------+ +-------+
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| IPI | --> | CPUINTC | <-- | Timer |
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+-----+ +---------+ +-------+
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^
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|
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+---------+ +-------+
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| LIOINTC | <-- | UARTs |
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+---------+ +-------+
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^
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|
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+-----------+
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| HTVECINTC |
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+-----------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
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| | |
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+---------+ +---------+ +---------+
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| PCH-LPC | | Devices | | Devices |
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+---------+ +---------+ +---------+
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^
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|
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+---------+
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| Devices |
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+---------+
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Extended IRQ model
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==================
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
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to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
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interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
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to CPUINTC directly::
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+-----+ +---------+ +-------+
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| IPI | --> | CPUINTC | <-- | Timer |
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+-----+ +---------+ +-------+
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^ ^
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| |
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+---------+ +---------+ +-------+
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| EIOINTC | | LIOINTC | <-- | UARTs |
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+---------+ +---------+ +-------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
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| | |
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+---------+ +---------+ +---------+
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| PCH-LPC | | Devices | | Devices |
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+---------+ +---------+ +---------+
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^
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|
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+---------+
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| Devices |
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+---------+
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Virtual Extended IRQ model
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==========================
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
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go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
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devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
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Extended I/O Interrupt Controller), and then go to CPUINTC directly::
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+-----+ +-------------------+ +-------+
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| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
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+-----+ +-------------------+ +-------+
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^
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|
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+-----------+
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| V-EIOINTC |
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+-----------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
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| | |
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+--------+ +---------+ +---------+
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| UARTs | | Devices | | Devices |
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+--------+ +---------+ +---------+
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Description
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-----------
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V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
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EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
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be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
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interrupts can be routed to up to 256 virtual cpus.
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With standard EIOINTC, interrupt routing setting includes two parts: eight
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bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
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For CPU selection there is four bits for EIOINTC node selection, four bits
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for EIOINTC CPU selection. Bitmap method is used for CPU selection and
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CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
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one EIOINTC node.
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With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
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there are two newly added registers with V-EIOINTC.
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EXTIOI_VIRT_FEATURES
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--------------------
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This register is read-only register, which indicates supported features with
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V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
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Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
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indicates that CPU Interrupt Pin selection can be normal method rather than
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bitmap method, so interrupt can be routed to IP0 - IP15.
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Feature EXTIOI_HAS_CPU_ENCODE is extension of V-EIOINTC. If it is 1, it
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indicates that CPU selection can be normal method rather than bitmap method,
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so interrupt can be routed to CPU0 - CPU255.
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EXTIOI_VIRT_CONFIG
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------------------
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This register is read-write register, for compatibility interrupt routed uses
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the default method which is the same with standard EIOINTC. If the bit is set
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with 1, it indicated HW to use normal method rather than bitmap method.
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Advanced Extended IRQ model
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===========================
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
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to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
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to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts
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go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
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+-----+ +-----------------------+ +-------+
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| IPI | --> | CPUINTC | <-- | Timer |
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+-----+ +-----------------------+ +-------+
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^ ^ ^
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| | |
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+---------+ +----------+ +---------+ +-------+
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| EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
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+---------+ +----------+ +---------+ +-------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
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| | |
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+---------+ +---------+ +---------+
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| Devices | | PCH-LPC | | Devices |
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+---------+ +---------+ +---------+
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^
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|
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+---------+
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| Devices |
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+---------+
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ACPI-related definitions
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========================
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CPUINTC::
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ACPI_MADT_TYPE_CORE_PIC;
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struct acpi_madt_core_pic;
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enum acpi_madt_core_pic_version;
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LIOINTC::
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ACPI_MADT_TYPE_LIO_PIC;
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struct acpi_madt_lio_pic;
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enum acpi_madt_lio_pic_version;
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EIOINTC::
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ACPI_MADT_TYPE_EIO_PIC;
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struct acpi_madt_eio_pic;
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enum acpi_madt_eio_pic_version;
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HTVECINTC::
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ACPI_MADT_TYPE_HT_PIC;
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struct acpi_madt_ht_pic;
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enum acpi_madt_ht_pic_version;
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PCH-PIC::
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ACPI_MADT_TYPE_BIO_PIC;
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struct acpi_madt_bio_pic;
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enum acpi_madt_bio_pic_version;
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PCH-MSI::
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ACPI_MADT_TYPE_MSI_PIC;
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struct acpi_madt_msi_pic;
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enum acpi_madt_msi_pic_version;
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PCH-LPC::
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ACPI_MADT_TYPE_LPC_PIC;
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struct acpi_madt_lpc_pic;
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enum acpi_madt_lpc_pic_version;
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References
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==========
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Documentation of Loongson-3A5000:
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
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Documentation of Loongson's LS7A chipset:
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
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.. Note::
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- CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
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in Section 7.4 of "LoongArch Reference Manual, Vol 1";
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- LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
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"Loongson 3A5000 Processor Reference Manual";
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- EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
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"Loongson 3A5000 Processor Reference Manual";
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- HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
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"Loongson 3A5000 Processor Reference Manual";
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- PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
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"Loongson 7A1000 Bridge User Manual";
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- PCH-LPC is "LPC Interrupts" described in Section 24.3 of
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"Loongson 7A1000 Bridge User Manual".
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
IRQ controller 계층
1-18현재 Loongson-3A5000 같은 LoongArch processor는 LS7A chipset과 함께 사용됩니다. IRQ chip에는 `CPUINTC`, `LIOINTC`, `EIOINTC`, `HTVECINTC`, `PCH-PIC`, `PCH-LPC`, `PCH-MSI`가 있습니다.
| Controller | Full name | Scope |
|---|---|---|
| `CPUINTC` | CPU Core Interrupt Controller | Per-core, CPU 내부 |
| `LIOINTC` | Legacy I/O Interrupt Controller | Per-package, CPU 내부 |
| `EIOINTC` | Extended I/O Interrupt Controller | Per-package, CPU 내부 |
| `HTVECINTC` | Hyper-Transport Vector Interrupt Controller | Per-package, CPU 내부 |
| `PCH-PIC` | LS7A Main Interrupt Controller | Chipset |
| `PCH-LPC` | LS7A LPC Interrupt Controller | Chipset |
| `PCH-MSI` | MSI Interrupt Controller | Chipset |
Controller들은 hierarchy로 연결되며 legacy, extended, virtual extended, advanced extended model을 구성합니다.
Legacy IRQ model
19-55`IPI`와 CPU local timer는 `CPUINTC`로 직접 갑니다. CPU UART는 `LIOINTC`, 나머지 device는 `PCH-PIC/PCH-LPC/PCH-MSI`에서 `HTVECINTC`로 모인 뒤 `LIOINTC`와 `CPUINTC`를 차례로 통과합니다. 원문 ASCII hierarchy는 요약의 Legacy flow로 구조화했습니다.
Extended IRQ model
56-87`IPI`와 timer는 `CPUINTC`, UART는 `LIOINTC`로 갑니다. 나머지 device interrupt는 PCH controller에서 `EIOINTC`로 모이고 `LIOINTC`를 거치지 않고 `CPUINTC`로 직접 갑니다. 원문 ASCII hierarchy는 Extended flow로 구조화했습니다.
Virtual Extended IRQ model
88-151Virtual model은 KVM hypervisor의 VM mode에서만 동작하는 `V-EIOINTC`를 사용합니다. `IPI`와 timer는 `CPUINTC`, UART는 `PCH-PIC`, 나머지는 `PCH-PIC/PCH-MSI`에서 `V-EIOINTC`로 모여 `CPUINTC(0-255 vCPU)`로 갑니다.
Standard `EIOINTC`는 최대 4 vCPU, `V-EIOINTC`는 최대 256 virtual CPU로 route할 수 있습니다. Standard routing은 CPU 선택 8 bits(4-bit node + 4-bit CPU)와 CPU IP 선택 4 bits를 bitmap으로 사용하므로 node 안에서 CPU0..CPU3, IP0..IP3만 고를 수 있습니다.
| Feature/config | 의미 |
|---|---|
| `EXTIOI_HAS_INT_ENCODE` | CPU Interrupt Pin을 bitmap 대신 normal encoding으로 선택해 IP0..IP15 route |
| `EXTIOI_HAS_CPU_ENCODE` | CPU를 normal encoding으로 선택해 CPU0..CPU255 route |
`EXTIOI_VIRT_FEATURES`는 지원 feature를 나타내는 read-only register입니다. `EXTIOI_VIRT_CONFIG`는 read-write이며 compatibility를 위해 기본 bitmap 방식을 사용하고 bit를 1로 설정하면 normal encoding을 선택합니다.
Advanced Extended IRQ model
152-183`IPI`와 timer는 `CPUINTC`, UART는 `LIOINTC`로 직접 갑니다. `PCH-MSI` interrupt는 `AVECINTC`를 거쳐 `CPUINTC`로 가고, 나머지 device interrupt는 `PCH-PIC/PCH-LPC`에서 `EIOINTC`로 모여 `CPUINTC`로 갑니다. 원문 ASCII hierarchy는 Advanced flow로 구조화했습니다.
ACPI 정의
184-228| Controller | MADT type | Structure | Version enum |
|---|---|---|---|
| `CPUINTC` | `ACPI_MADT_TYPE_CORE_PIC` | `struct acpi_madt_core_pic` | `enum acpi_madt_core_pic_version` |
| `LIOINTC` | `ACPI_MADT_TYPE_LIO_PIC` | `struct acpi_madt_lio_pic` | `enum acpi_madt_lio_pic_version` |
| `EIOINTC` | `ACPI_MADT_TYPE_EIO_PIC` | `struct acpi_madt_eio_pic` | `enum acpi_madt_eio_pic_version` |
| `HTVECINTC` | `ACPI_MADT_TYPE_HT_PIC` | `struct acpi_madt_ht_pic` | `enum acpi_madt_ht_pic_version` |
| `PCH-PIC` | `ACPI_MADT_TYPE_BIO_PIC` | `struct acpi_madt_bio_pic` | `enum acpi_madt_bio_pic_version` |
| `PCH-MSI` | `ACPI_MADT_TYPE_MSI_PIC` | `struct acpi_madt_msi_pic` | `enum acpi_madt_msi_pic_version` |
| `PCH-LPC` | `ACPI_MADT_TYPE_LPC_PIC` | `struct acpi_madt_lpc_pic` | `enum acpi_madt_lpc_pic_version` |
참고 자료
229-256- Loongson-3A5000 manual English
https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf - Loongson-7A1000 manual English
https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf
- `CPUINTC`: LoongArch Reference Manual Vol.1 7.4절의 `CSR.ECFG/CSR.ESTAT`
- `LIOINTC`: Loongson 3A5000 manual 11.1절 Legacy I/O Interrupts
- `EIOINTC`: Loongson 3A5000 manual 11.2절 Extended I/O Interrupts
- `HTVECINTC`: Loongson 3A5000 manual 14.3절 HyperTransport Interrupts
- `PCH-PIC/PCH-MSI`: Loongson 7A1000 manual 5절 Interrupt Controller
- `PCH-LPC`: Loongson 7A1000 manual 24.3절 LPC Interrupts
요약과 해설
irq-chip-model.rst:1-256네 원문 ASCII hierarchy를 각각 같은 routing 의미의 flow로 다시 그렸습니다. 차이는 device interrupt를 `HTVECINTC`, `EIOINTC`, `V-EIOINTC`, `AVECINTC` 중 어디에서 모아 `CPUINTC`로 전달하는지입니다.
HTVECINTC와 LIOINTC를 연속으로 통과합니다.
EIOINTC가 CPUINTC로 직접 전달합니다.
V-EIOINTC가 최대 256 vCPU로 route합니다.
MSI를 AVECINTC 전용 경로로 분리합니다.