요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
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=========================================================
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NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)
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=========================================================
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The NVIDIA Tegra SoC includes various system PMUs to measure key performance
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metrics like memory bandwidth, latency, and utilization:
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* Scalable Coherency Fabric (SCF)
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* NVLink-C2C0
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* NVLink-C2C1
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* CNVLink
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* PCIE
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PMU Driver
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----------
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The PMUs in this document are based on ARM CoreSight PMU Architecture as
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described in document: ARM IHI 0091. Since this is a standard architecture, the
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PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
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the available events and configuration of each PMU in sysfs. Please see the
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sections below to get the sysfs path of each PMU. Like other uncore PMU drivers,
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the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
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the PMU event. There is also "associated_cpus" sysfs attribute, which contains a
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list of CPUs associated with the PMU instance.
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.. _SCF_PMU_Section:
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SCF PMU
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-------
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The SCF PMU monitors system level cache events, CPU traffic, and
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strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
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:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU
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traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 in socket 0::
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perf stat -a -e nvidia_scf_pmu_0/event=0x0/
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* Count event id 0x0 in socket 1::
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perf stat -a -e nvidia_scf_pmu_1/event=0x0/
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NVLink-C2C0 PMU
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--------------------
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The NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
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NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
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varies dependent on the chip configuration:
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* NVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC.
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In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.
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* NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.
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In this config, the PMU captures read and relaxed ordered (RO) writes from
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PCIE device of the remote SoC.
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Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about
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the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 from the GPU/CPU connected with socket 0::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/
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* Count event id 0x0 from the GPU/CPU connected with socket 1::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/
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* Count event id 0x0 from the GPU/CPU connected with socket 2::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/
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* Count event id 0x0 from the GPU/CPU connected with socket 3::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/
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The NVLink-C2C has two ports that can be connected to one GPU (occupying both
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ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
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parameter to select the port(s) to monitor. Each bit represents the port number,
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e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
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PMU will monitor both ports by default if not specified.
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Example for port filtering:
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* Count event id 0x0 from the GPU connected with socket 0 on port 0::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/
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* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/
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NVLink-C2C1 PMU
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-------------------
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The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
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NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU
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traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
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Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about
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the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 from the GPU connected with socket 0::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/
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* Count event id 0x0 from the GPU connected with socket 1::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/
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* Count event id 0x0 from the GPU connected with socket 2::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/
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* Count event id 0x0 from the GPU connected with socket 3::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/
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The NVLink-C2C has two ports that can be connected to one GPU (occupying both
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ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
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parameter to select the port(s) to monitor. Each bit represents the port number,
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e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
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PMU will monitor both ports by default if not specified.
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Example for port filtering:
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* Count event id 0x0 from the GPU connected with socket 0 on port 0::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/
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* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/
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CNVLink PMU
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---------------
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The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
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to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
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(RO) write traffic. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
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for more info about the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>.
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Each SoC socket can be connected to one or more sockets via CNVLink. The user can
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use "rem_socket" bitmap parameter to select the remote socket(s) to monitor.
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Each bit represents the socket number, e.g. "rem_socket=0xE" corresponds to
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socket 1 to 3. The PMU will monitor all remote sockets by default if not
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specified.
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/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
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shows the valid bits that can be set in the "rem_socket" parameter.
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The PMU can not distinguish the remote traffic initiator, therefore it does not
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provide filter to select the traffic source to monitor. It reports combined
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traffic from remote GPU and PCIE devices.
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Example usage:
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* Count event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0::
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perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/
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* Count event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1::
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perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/
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* Count event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2::
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perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/
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* Count event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3::
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perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/
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PCIE PMU
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------------
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The PCIE PMU monitors all read/write traffic from PCIE root ports to
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local/remote memory. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
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for more info about the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>.
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Each SoC socket can support multiple root ports. The user can use
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"root_port" bitmap parameter to select the port(s) to monitor, i.e.
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"root_port=0xF" corresponds to root port 0 to 3. The PMU will monitor all root
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ports by default if not specified.
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/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
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shows the valid bits that can be set in the "root_port" parameter.
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Example usage:
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* Count event id 0x0 from root port 0 and 1 of socket 0::
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perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/
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* Count event id 0x0 from root port 0 and 1 of socket 1::
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perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/
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.. _NVIDIA_Uncore_PMU_Traffic_Coverage_Section:
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Traffic Coverage
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----------------
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The PMU traffic coverage may vary dependent on the chip configuration:
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* **NVIDIA Grace Hopper Superchip**: Hopper GPU is connected with Grace SoC.
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Example configuration with two Grace SoCs::
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********************************* *********************************
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* SOCKET-A * * SOCKET-B *
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* * * *
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* :::::::: * * :::::::: *
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* : PCIE : * * : PCIE : *
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* :::::::: * * :::::::: *
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* | * * | *
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* | * * | *
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* ::::::: ::::::::: * * ::::::::: ::::::: *
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* : : : : * * : : : : *
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* : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
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* : : C2C : SoC : * * : SoC : C2C : : *
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* ::::::: ::::::::: * * ::::::::: ::::::: *
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* | | * * | | *
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* | | * * | | *
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* &&&&&&&& &&&&&&&& * * &&&&&&&& &&&&&&&& *
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* & GMEM & & CMEM & * * & CMEM & & GMEM & *
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* &&&&&&&& &&&&&&&& * * &&&&&&&& &&&&&&&& *
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* * * *
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********************************* *********************************
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GMEM = GPU Memory (e.g. HBM)
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CMEM = CPU Memory (e.g. LPDDR5X)
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|
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| Following table contains traffic coverage of Grace SoC PMU in socket-A:
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::
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| | Source |
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+ +-------+-----------+-----------+-----+----------+----------+
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| Destination | |GPU ATS |GPU Not-ATS| | Socket-B | Socket-B |
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| |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
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| | |EGM | | | | |
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+==============+=======+===========+===========+=====+==========+==========+
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| Local | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU | CNVLink |
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| SYSRAM/CMEM | PMU |PMU |PMU | PMU | | PMU |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| Local GMEM | PCIE | N/A |NVLink-C2C1| SCF | SCF PMU | CNVLink |
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| | PMU | |PMU | PMU | | PMU |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| Remote | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | |
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| SYSRAM/CMEM | PMU |PMU |PMU | PMU | N/A | N/A |
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| over CNVLink | | | | | | |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| Remote GMEM | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | |
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| over CNVLink | PMU |PMU |PMU | PMU | N/A | N/A |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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PCIE1 traffic represents strongly ordered (SO) writes.
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PCIE2 traffic represents reads and relaxed ordered (RO) writes.
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* **NVIDIA Grace CPU Superchip**: two Grace CPU SoCs are connected.
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Example configuration with two Grace SoCs::
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******************* *******************
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* SOCKET-A * * SOCKET-B *
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* * * *
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* :::::::: * * :::::::: *
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* : PCIE : * * : PCIE : *
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* :::::::: * * :::::::: *
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* | * * | *
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* | * * | *
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* ::::::::: * * ::::::::: *
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* : : * * : : *
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* : Grace :<--------NVLink------->: Grace : *
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* : SoC : * C2C * : SoC : *
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* ::::::::: * * ::::::::: *
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* | * * | *
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* | * * | *
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* &&&&&&&& * * &&&&&&&& *
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* & CMEM & * * & CMEM & *
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* &&&&&&&& * * &&&&&&&& *
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* * * *
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******************* *******************
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GMEM = GPU Memory (e.g. HBM)
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CMEM = CPU Memory (e.g. LPDDR5X)
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|
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| Following table contains traffic coverage of Grace SoC PMU in socket-A:
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::
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+-----------------+-----------+---------+----------+-------------+
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| | Source |
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+ +-----------+---------+----------+-------------+
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| Destination | | | Socket-B | Socket-B |
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| | PCI R/W | CPU | CPU/PCIE1| PCIE2 |
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| | | | | |
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+=================+===========+=========+==========+=============+
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| Local | PCIE PMU | SCF PMU | SCF PMU | NVLink-C2C0 |
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| SYSRAM/CMEM | | | | PMU |
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+-----------------+-----------+---------+----------+-------------+
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| Remote | | | | |
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| SYSRAM/CMEM | PCIE PMU | SCF PMU | N/A | N/A |
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| over NVLink-C2C | | | | |
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+-----------------+-----------+---------+----------+-------------+
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PCIE1 traffic represents strongly ordered (SO) writes.
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PCIE2 traffic represents reads and relaxed ordered (RO) writes.
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
Tegra SoC system PMU
1-12`NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)`은 memory bandwidth, latency, utilization 같은 핵심 performance metrics를 측정합니다.
System PMU는 `Scalable Coherency Fabric (SCF)`, NVLink-C2C0, NVLink-C2C1, CNVLink, PCIE로 구성됩니다.
| PMU | 주요 traffic coverage |
|---|---|
| SCF | System cache, CPU, strongly-ordered PCIE write traffic |
| NVLink-C2C0 | ATS translated/EGM GPU 또는 remote Grace PCIE2 traffic |
| NVLink-C2C1 | Untranslated GPU traffic |
| CNVLink | Remote socket GPU/PCIE traffic to local memory |
| PCIE | Root port read/write traffic to local/remote memory |
CoreSight 공통 driver와 CPU affinity
13-24이 문서의 PMU는 `ARM IHI 0091`에 설명된 `ARM CoreSight PMU Architecture`를 기반으로 하며, 표준 architecture이므로 공통 driver `arm-cs-arch-pmu`가 관리합니다.
Driver는 각 PMU의 available event와 configuration을 sysfs에 설명합니다.
| 항목 | 의미 |
|---|---|
| Architecture | `ARM CoreSight PMU Architecture`, `ARM IHI 0091` |
| `cpumask` | PMU event를 처리하는 CPU ID |
| `associated_cpus` | 해당 PMU instance와 연관된 CPU 목록 |
SCF cache와 CPU/PCIE traffic
25-48`SCF PMU`는 system level cache events, CPU traffic, local/remote memory로 향하는 strongly-ordered (SO) PCIE write traffic을 감시합니다.
Event와 configuration option은 `/sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>`에 있습니다.
| 대상 | 경로 또는 event |
|---|---|
| Sysfs | `/sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>` |
| Socket 0 | `nvidia_scf_pmu_0/event=0x0/` |
| Socket 1 | `nvidia_scf_pmu_1/event=0x0/` |
Socket 0과 socket 1에서 event ID `0x0`을 세는 예제입니다.
perf stat -a -e nvidia_scf_pmu_0/event=0x0/perf stat -a -e nvidia_scf_pmu_1/event=0x0/NVLink-C2C0 translated/remote traffic
49-104`NVLink-C2C0 PMU`는 NVLink-C2C (Chip-2-Chip) interconnect로 연결된 GPU/CPU에서 들어오는 traffic을 감시하며 chip configuration에 따라 포착 대상이 달라집니다.
| Configuration | 포착 traffic |
|---|---|
| NVIDIA Grace Hopper Superchip | Hopper GPU의 GPU ATS translated 또는 EGM traffic |
| NVIDIA Grace CPU Superchip | Remote SoC PCIE device의 read와 relaxed ordered (RO) write |
Event와 configuration option은 `/sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>`에 있습니다. Socket 0-3에 연결된 GPU/CPU의 event ID `0x0`을 세는 예제입니다.
perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/NVLink-C2C는 한 GPU가 두 ports를 모두 차지하거나 GPU 두 개가 port 하나씩을 사용할 수 있습니다. `port` bitmap의 각 bit가 port 번호를 나타냅니다.
| `port` | 감시 범위 |
|---|---|
| 생략 | 두 port 모두 감시 |
| `port=0x1` | Port 0 |
| `port=0x3` | Port 0과 port 1 |
Socket 0의 port 0만, 또는 port 0과 1을 함께 고르는 예제입니다.
perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/NVLink-C2C1 untranslated GPU traffic
105-150`NVLink-C2C1 PMU`는 NVLink-C2C로 연결된 GPU의 incoming untranslated GPU traffic을 감시합니다. 이는 ATS translated traffic을 포착하는 NVLink-C2C0 PMU와 대비됩니다.
| 관점 | 내용 |
|---|---|
| Traffic | Untranslated GPU traffic |
| Contrast | NVLink-C2C0은 ATS translated traffic |
| Sysfs | `/sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>` |
Socket 0-3에 연결된 GPU의 event ID `0x0`을 세는 예제입니다.
perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/C2C1도 C2C0과 같은 두-port 구조와 `port` bitmap 의미를 사용하며 option을 생략하면 두 ports를 모두 감시합니다.
Socket 0의 port 0만, 또는 port 0과 1을 함께 고르는 예제입니다.
perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/Remote socket bitmap과 결합 traffic
151-192`CNVLink PMU`는 remote socket의 GPU와 PCIE device에서 local memory로 들어오는 traffic을 감시합니다. PCIE traffic 중 read와 relaxed ordered (RO) write를 포착합니다.
Event와 configuration option은 `/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>`에 있습니다. `rem_socket` bitmap의 bit가 remote socket 번호를 나타내며 생략하면 모든 remote sockets를 감시합니다.
`/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket`에서 `rem_socket`에 설정할 수 있는 valid bits를 확인합니다.
CNVLink PMU는 remote traffic initiator를 구분하지 못하므로 source 선택 filter를 제공하지 않고 remote GPU와 PCIE device의 combined traffic을 보고합니다.
| Bitmap | Traffic 방향 |
|---|---|
| `rem_socket=0xE` | Remote socket 1, 2, 3 -> socket 0 |
| `rem_socket=0xD` | Remote socket 0, 2, 3 -> socket 1 |
| `rem_socket=0xB` | Remote socket 0, 1, 3 -> socket 2 |
| `rem_socket=0x7` | Remote socket 0, 1, 2 -> socket 3 |
perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/Root port read/write traffic
193-219`PCIE PMU`는 PCIE root ports에서 local/remote memory로 향하는 모든 read/write traffic을 감시합니다.
Event와 configuration option은 `/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>`에 있습니다. `root_port` bitmap으로 socket의 root port를 고르며 생략하면 모두 감시합니다.
`/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port`에서 valid bits를 확인합니다.
| Bitmap | Root port |
|---|---|
| 생략 | Socket의 모든 root ports |
| `root_port=0xF` | Root port 0-3 |
| `root_port=0x3` | Root port 0과 1 |
Socket 0과 socket 1에서 root port 0과 1을 고르는 예제입니다.
perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/Grace Hopper Superchip traffic matrix
220-283원문의 `Traffic Coverage`에서 `NVIDIA Grace Hopper Superchip`은 Hopper GPU가 Grace SoC와 연결됩니다. 예제 topology는 socket마다 PCIE, Grace SoC/CMEM, GPU/GMEM을 두고, socket 내부는 NVLink-C2C, 두 Grace SoC 사이는 CNVLink로 연결합니다.
SOCKET-A PCIE -> Grace SoC A→GPU A / GMEM <-- NVLink-C2C --> Grace SoC A / CMEM→Grace SoC A <-- CNVLink --> Grace SoC B→Grace SoC B / CMEM <-- NVLink-C2C --> GPU B / GMEM→Grace SoC B <- SOCKET-B PCIE
각 socket의 GPU/GMEM, Grace SoC/CMEM, PCIE와 socket 사이 CNVLink 연결을 구조화했습니다.
`GMEM`은 GPU Memory (예: HBM), `CMEM`은 CPU Memory (예: LPDDR5X)입니다. Socket-A Grace SoC PMU가 source와 destination 조합별로 담당하는 coverage는 다음과 같습니다.
DestinationPCI R/WGPU ATS translated, EGMGPU Not-ATS translatedCPUSocket-B CPU/PCIE1Socket-B GPU/PCIE2
Local SYSRAM/CMEMPCIE PMUNVLink-C2C0 PMUNVLink-C2C1 PMUSCF PMUSCF PMUCNVLink PMU
Local GMEMPCIE PMUN/ANVLink-C2C1 PMUSCF PMUSCF PMUCNVLink PMU
Remote SYSRAM/CMEM over CNVLinkPCIE PMUNVLink-C2C0 PMUNVLink-C2C1 PMUSCF PMUN/AN/A
Remote GMEM over CNVLinkPCIE PMUNVLink-C2C0 PMUNVLink-C2C1 PMUSCF PMUN/AN/A
Destination과 source 조합마다 event를 관찰할 PMU를 원문 matrix와 동일하게 배치했습니다.
| Remote PCIE traffic | Ordering |
|---|---|
| PCIE1 | Strongly ordered (SO) writes |
| PCIE2 | Reads와 relaxed ordered (RO) writes |
Grace CPU Superchip traffic matrix
284-333`NVIDIA Grace CPU Superchip`에서는 Grace CPU SoC 두 개를 NVLink-C2C로 연결합니다. 각 socket에는 PCIE와 Grace SoC/CMEM이 있고 GPU/GMEM은 없습니다.
SOCKET-A PCIE -> Grace SoC A→Grace SoC A -> CMEM A→Grace SoC A <-- NVLink-C2C --> Grace SoC B→Grace SoC B -> CMEM B→Grace SoC B <- SOCKET-B PCIE
각 socket의 PCIE, Grace SoC, CMEM과 socket 사이 NVLink-C2C 연결을 구조화했습니다.
`GMEM`은 GPU Memory (예: HBM), `CMEM`은 CPU Memory (예: LPDDR5X)라는 정의를 유지합니다. Socket-A Grace SoC PMU coverage는 다음과 같습니다.
DestinationPCI R/WCPUSocket-B CPU/PCIE1Socket-B PCIE2
Local SYSRAM/CMEMPCIE PMUSCF PMUSCF PMUNVLink-C2C0 PMU
Remote SYSRAM/CMEM over NVLink-C2CPCIE PMUSCF PMUN/AN/A
Local/remote SYSRAM/CMEM destination과 source별 담당 PMU를 원문 matrix와 동일하게 배치했습니다.
`PCIE1` traffic은 strongly ordered (SO) writes이고 `PCIE2` traffic은 `reads and relaxed ordered (RO) writes`입니다.
운영 요약
nvidia-pmu.rst:1-333Traffic source, destination, translation 상태와 chip configuration을 먼저 구분한 뒤 SCF, C2C0, C2C1, CNVLink, PCIE PMU를 선택하고 socket/port bitmap을 적용합니다.