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Linux 6.18.37 · Administration / Performance

Freescale i.MX8 DDR Performance Monitoring Unit

i.MX8 DDR PMU counter와 기본·enhanced·port/channel AXI filter를 설명합니다.

Source pathDocumentation/admin-guide/perf/imx-ddr.rst
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

운영 요약

imx-ddr.rst:1-100

Controller 가장자리의 4개 counter를 perf로 측정하고, `caps`에 따라 AXI ID/mask filter 또는 counter별 ID/port/channel filter를 적용합니다.

관점핵심
CounterController edge의 4 x 32 bit counters
Counter 0항상 `time` count; expiry 시 lock과 interrupt
Counter 1-3Overflow 뒤에도 계속 count하며 interrupt 없음
CSV modes`0x41` axid-read, `0x42` axid-write
Filter capability`filter`, `enhanced_filter`, `super_filter`
Perf`cycles`, `read`, `write`, AXI ID/mask/channel event

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 =====================================================
2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
3 =====================================================
4
5 There are no performance counters inside the DRAM controller, so performance
6 signals are brought out to the edge of the controller where a set of 4 x 32 bit
7 counters is implemented. This is controlled by the CSV modes programmed in counter
8 control register which causes a large number of PERF signals to be generated.
9
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
12 “time” and when expired causes a lock on itself and the other counters and an
13 interrupt is raised. If any other counter overflows, it continues counting, and
14 no interrupt is raised.
15
16 The "format" directory describes format of the config (event ID) and config1/2
17 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/
18 devices/imx8_ddr0/format/. The "events" directory describes the events types
19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
20 devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
22
23 .. code-block:: bash
24
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
27
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
29 to count reading or writing matches filter setting. Filter setting is various
30 from different DRAM controller implementations, which is distinguished by quirks
31 in the driver. You also can dump info from userspace, "caps" directory show the
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
33 un-supported, and value 1 for supported.
34
35 * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0).
36 Filter is defined with two configuration parts:
37 --AXI_ID defines AxID matching value.
38 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
39
40 - 0: corresponding bit is masked.
41 - 1: corresponding bit is not masked, i.e. used to do the matching.
42
43 AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
44 When non-masked bits are matching corresponding AXI_ID bits then counter is
45 incremented. Perf counter is incremented if::
46
47 AxID && AXI_MASKING == AXI_ID && AXI_MASKING
48
49 This filter doesn't support filter different AXI ID for axid-read and axid-write
50 event at the same time as this filter is shared between counters.
51
52 .. code-block:: bash
53
54 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
55 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
56
57 .. note::
58
59 axi_mask is inverted in userspace(i.e. set bits are bits to mask), and
60 it will be reverted in driver automatically. so that the user can just specify
61 axi_id to monitor a specific id, rather than having to specify axi_mask.
62
63 .. code-block:: bash
64
65 perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
66
67 * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0).
68 This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits
69 counting the number of bytes (as opposed to the number of bursts) from DDR
70 read and write transactions concurrently with another set of data counters.
71
72 * With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1).
73 There is a limitation in previous AXI filter, it cannot filter different IDs
74 at the same time as the filter is shared between counters. This quirk is the
75 extension of AXI ID filter. One improvement is that counter 1-3 has their own
76 filter, means that it supports concurrently filter various IDs. Another
77 improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
78 selecting address channel or data channel.
79
80 Filter is defined with 2 configuration registers per counter 1-3.
81 --Counter N MASK COMP register - including AXI_ID and AXI_MASKING.
82 --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
83
84 - 0: address channel
85 - 1: data channel
86
87 PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved
88 which should be 0.
89
90 .. code-block:: bash
91
92 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
93 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
94
95 .. note::
96
97 axi_channel is inverted in userspace, and it will be reverted in driver
98 automatically. So that users do not need specify axi_channel if want to
99 monitor data channel from DDR transactions, since data channel is more
100 meaningful.
101

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

DRAM controller 외부 counter 구조

1-14

DRAM controller 내부에는 performance counter가 없습니다. 따라서 performance signal을 controller 가장자리로 꺼내 4 x 32 bit counters로 구현합니다.

Counter control register에 program한 CSV modes가 많은 PERF signal을 생성하고, 각 counter의 config registers가 셀 값을 선택합니다.

Counter 0은 항상 `“time”`을 셉니다. Counter 0이 expire하면 자신과 다른 counter를 lock하고 interrupt를 발생시킵니다. 다른 counter는 overflow해도 계속 세며 interrupt를 발생시키지 않습니다.

Sysfs event와 AXI capability

15-33
Directory설명
`format``config` event ID와 `config1/2` AXI filter setting
`events`Hardware가 지원하고 perf에서 사용할 event type
`caps`DDR PMU에 구현된 AXI filter feature

`format`은 `perf_event_attr`의 `config` event ID와 `config1/2` AXI filter setting 형식을 설명합니다. 경로는 `/sys/bus/event_source/devices/imx8_ddr0/format/`입니다.

`events`는 `/sys/bus/event_source/devices/imx8_ddr0/events/`에서 perf가 사용할 hardware event type을 제공합니다. `caps`는 원문 경로 `/sys/bus/events_source/devices/imx8_ddr0/caps/`에서 filter feature를 설명합니다.

perf stat -a -e imx8_ddr0/cycles/ cmd
perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd

AXI filtering은 CSV mode `0x41` (`axid-read`)과 `0x42` (`axid-write`)에서만 filter setting과 일치하는 read 또는 write를 셉니다. DRAM controller 구현별 차이는 driver quirk로 구분합니다.

Capability의미
`filter``DDR_CAP_AXI_ID_FILTER` 지원 여부
`enhanced_filter`Byte counting 확장 지원 여부
`super_filter`Counter별 ID/port/channel filter 지원 여부

`caps` 값 0은 미지원, 1은 지원을 뜻합니다.

AXI ID와 mask filter

34-66
QuirkCapability 조합
`DDR_CAP_AXI_ID_FILTER``filter: 1, enhanced_filter: 0, super_filter: 0`
`DDR_CAP_AXI_ID_FILTER_ENHANCED``filter: 1, enhanced_filter: 1, super_filter: 0`
`DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER``filter: 0, enhanced_filter: 0, super_filter: 1`

`DDR_CAP_AXI_ID_FILTER`에서는 `AXI_ID`가 AxID matching value를, `AXI_MASKING`이 matching에 의미 있는 AxID bit를 정의합니다.

`AXI_MASKING` bitMatching 동작
`0`해당 AxID bit를 mask하여 비교하지 않음
`1`해당 AxID bit를 mask하지 않고 matching에 사용

`AXI_ID`와 `AXI_MASKING`은 performance counter의 DPCR1 register에 mapping됩니다. Mask하지 않은 bit가 해당 `AXI_ID` bit와 일치할 때 counter가 증가합니다.

AxID && AXI_MASKING == AXI_ID && AXI_MASKING

Filter를 counter들이 공유하므로 `axid-read`와 `axid-write` event에 서로 다른 AXI ID를 동시에 적용할 수 없습니다.

perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd

Userspace의 `axi_mask` 의미는 반전되어 set bit가 mask할 bit입니다. Driver가 자동으로 다시 반전하므로 특정 ID만 감시할 때는 `axi_mask` 없이 `axi_id`만 지정할 수 있습니다.

perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12

Burst 대신 byte count

67-71

`DDR_CAP_AXI_ID_FILTER_ENHANCED`는 기본 `DDR_CAP_AXI_ID_FILTER`의 확장입니다. 다른 data counter set과 동시에 DDR read/write transaction의 burst 수 (`number of bursts`)가 아니라 byte 수 (`number of bytes`)를 셀 수 있습니다.

Counter별 ID, port, channel

72-100

`DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER`는 counter가 filter를 공유해 서로 다른 ID를 동시에 거르지 못하던 이전 AXI filter의 제한을 확장합니다.

`counter 1-3`은 각자 filter를 가지므로 여러 ID를 동시에 거를 수 있고, AXI PORT와 CHANNEL도 선택할 수 있습니다. `address channel` 또는 `data channel`을 고를 수 있습니다.

Counter별 register포함 field
Counter N MASK COMP`AXI_ID`, `AXI_MASKING`
Counter N MUX CNTL`AXI CHANNEL`, `AXI PORT`
`axi_channel` hardware 값Channel
`0`Address channel
`1`Data channel

DDR subsystem에는 port0 하나만 있으므로 `axi_port`는 reserved이며 0이어야 합니다.

perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd

Userspace의 `axi_channel`도 반전되어 driver가 자동으로 되돌립니다. DDR transaction에서 더 의미 있는 data channel을 감시하려면 `axi_channel`을 생략할 수 있습니다.