요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
Memdev identity, capacity와 QoS
sysfs-bus-cxl:11-110Firmware revision, mailbox payload cap, LSA·volatile·persistent capacities, partition별 QoS classes, serial number와 NUMA affinity를 제공합니다.
Memdev security와 firmware upload
sysfs-bus-cxl:113-169Security state를 poll하고 disabled memdev에서 sanitize 또는 encryption-key erase를 수행하며 firmware uploader interfaces를 제공합니다.
CXL device identity와 port topology
sysfs-bus-cxl:172-245Uevent identity, uport·dport·parent_dport symlinks와 active decoder count로 CXL hierarchy와 destructive-operation eligibility를 나타냅니다.
Decoder windows, targets와 capabilities
sysfs-bus-cxl:248-333Decoder instance identity, decode window, lock state, ordered targets, memory-type capabilities, switch target type와 endpoint CDAT data를 설명합니다.
Endpoint decoder DPA와 interleave
sysfs-bus-cxl:336-410Endpoint decoder mode, DPA base·size allocation ordering, HPA interleave ways와 granularity를 정의합니다.
Root decoder region lifecycle
sysfs-bus-cxl:413-450Root decoder에서 pmem·ram region IDs를 atomic하게 생성하고 idle region을 삭제하며 QoS class compatibility를 확인합니다.
Region configuration과 commit
sysfs-bus-cxl:453-557Region UUID, interleave, size·resource, endpoint targets를 구성한 뒤 spec-mandated decoder order로 hardware commit합니다.
Poison, access performance와 dirty shutdown
sysfs-bus-cxl:560-617Poison list retrieval, region aggregate bandwidth·worst latency와 persistent dirty-shutdown count를 제공합니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
1
What: /sys/bus/cxl/flush
2
Date: January, 2022
3
KernelVersion: v5.18
4
Contact: [email protected]
5
Description:
6
(WO) If userspace manually unbinds a port the kernel schedules
7
all descendant memdevs for unbind. Writing '1' to this attribute
8
flushes that work.
11
What: /sys/bus/cxl/devices/memX/firmware_version
12
Date: December, 2020
13
KernelVersion: v5.12
14
Contact: [email protected]
15
Description:
16
(RO) "FW Revision" string as reported by the Identify
17
Memory Device Output Payload in the CXL-2.0
18
specification.
21
What: /sys/bus/cxl/devices/memX/payload_max
22
Date: December, 2020
23
KernelVersion: v5.12
24
Contact: [email protected]
25
Description:
26
(RO) Maximum size (in bytes) of the mailbox command payload
27
registers. Linux caps this at 1MB if the device reports a
28
larger size.
31
What: /sys/bus/cxl/devices/memX/label_storage_size
32
Date: May, 2021
33
KernelVersion: v5.13
34
Contact: [email protected]
35
Description:
36
(RO) Size (in bytes) of the Label Storage Area (LSA).
39
What: /sys/bus/cxl/devices/memX/ram/size
40
Date: December, 2020
41
KernelVersion: v5.12
42
Contact: [email protected]
43
Description:
44
(RO) "Volatile Only Capacity" as bytes. Represents the
45
identically named field in the Identify Memory Device Output
46
Payload in the CXL-2.0 specification.
49
What: /sys/bus/cxl/devices/memX/ram/qos_class
50
Date: May, 2023
51
KernelVersion: v6.8
52
Contact: [email protected]
53
Description:
54
(RO) For CXL host platforms that support "QoS Telemetry"
55
this attribute conveys a comma delimited list of platform
56
specific cookies that identifies a QoS performance class
57
for the volatile partition of the CXL mem device. These
58
class-ids can be compared against a similar "qos_class"
59
published for a root decoder. While it is not required
60
that the endpoints map their local memory-class to a
61
matching platform class, mismatches are not recommended
62
and there are platform specific performance related
63
side-effects that may result. First class-id is displayed.
66
What: /sys/bus/cxl/devices/memX/pmem/size
67
Date: December, 2020
68
KernelVersion: v5.12
69
Contact: [email protected]
70
Description:
71
(RO) "Persistent Only Capacity" as bytes. Represents the
72
identically named field in the Identify Memory Device Output
73
Payload in the CXL-2.0 specification.
76
What: /sys/bus/cxl/devices/memX/pmem/qos_class
77
Date: May, 2023
78
KernelVersion: v6.8
79
Contact: [email protected]
80
Description:
81
(RO) For CXL host platforms that support "QoS Telemetry"
82
this attribute conveys a comma delimited list of platform
83
specific cookies that identifies a QoS performance class
84
for the persistent partition of the CXL mem device. These
85
class-ids can be compared against a similar "qos_class"
86
published for a root decoder. While it is not required
87
that the endpoints map their local memory-class to a
88
matching platform class, mismatches are not recommended
89
and there are platform specific performance related
90
side-effects that may result. First class-id is displayed.
93
What: /sys/bus/cxl/devices/memX/serial
94
Date: January, 2022
95
KernelVersion: v5.18
96
Contact: [email protected]
97
Description:
98
(RO) 64-bit serial number per the PCIe Device Serial Number
99
capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
100
Memory Device PCIe Capabilities and Extended Capabilities.
103
What: /sys/bus/cxl/devices/memX/numa_node
104
Date: January, 2022
105
KernelVersion: v5.18
106
Contact: [email protected]
107
Description:
108
(RO) If NUMA is enabled and the platform has affinitized the
109
host PCI device for this memory device, emit the CPU node
110
affinity for this device.
113
What: /sys/bus/cxl/devices/memX/security/state
114
Date: June, 2023
115
KernelVersion: v6.5
116
Contact: [email protected]
117
Description:
118
(RO) Reading this file will display the CXL security state for
119
that device. Such states can be: 'disabled', 'sanitize', when
120
a sanitization is currently underway; or those available only
121
for persistent memory: 'locked', 'unlocked' or 'frozen'. This
122
sysfs entry is select/poll capable from userspace to notify
123
upon completion of a sanitize operation.
126
What: /sys/bus/cxl/devices/memX/security/sanitize
127
Date: June, 2023
128
KernelVersion: v6.5
129
Contact: [email protected]
130
Description:
131
(WO) Write a boolean 'true' string value to this attribute to
132
sanitize the device to securely re-purpose or decommission it.
133
This is done by ensuring that all user data and meta-data,
134
whether it resides in persistent capacity, volatile capacity,
135
or the LSA, is made permanently unavailable by whatever means
136
is appropriate for the media type. This functionality requires
137
the device to be disabled, that is, not actively decoding any
138
HPA ranges. This permits avoiding explicit global CPU cache
139
management, relying instead for it to be done when a region
140
transitions between software programmed and hardware committed
141
states. If this file is not present, then there is no hardware
142
support for the operation.
145
What /sys/bus/cxl/devices/memX/security/erase
146
Date: June, 2023
147
KernelVersion: v6.5
148
Contact: [email protected]
149
Description:
150
(WO) Write a boolean 'true' string value to this attribute to
151
secure erase user data by changing the media encryption keys for
152
all user data areas of the device. This functionality requires
153
the device to be disabled, that is, not actively decoding any
154
HPA ranges. This permits avoiding explicit global CPU cache
155
management, relying instead for it to be done when a region
156
transitions between software programmed and hardware committed
157
states. If this file is not present, then there is no hardware
158
support for the operation.
161
What: /sys/bus/cxl/devices/memX/firmware/
162
Date: April, 2023
163
KernelVersion: v6.5
164
Contact: [email protected]
165
Description:
166
(RW) Firmware uploader mechanism. The different files under
167
this directory can be used to upload and activate new
168
firmware for CXL devices. The interfaces under this are
169
documented in sysfs-class-firmware.
172
What: /sys/bus/cxl/devices/*/devtype
173
Date: June, 2021
174
KernelVersion: v5.14
175
Contact: [email protected]
176
Description:
177
(RO) CXL device objects export the devtype attribute which
178
mirrors the same value communicated in the DEVTYPE environment
179
variable for uevents for devices on the "cxl" bus.
182
What: /sys/bus/cxl/devices/*/modalias
183
Date: December, 2021
184
KernelVersion: v5.18
185
Contact: [email protected]
186
Description:
187
(RO) CXL device objects export the modalias attribute which
188
mirrors the same value communicated in the MODALIAS environment
189
variable for uevents for devices on the "cxl" bus.
192
What: /sys/bus/cxl/devices/portX/uport
193
Date: June, 2021
194
KernelVersion: v5.14
195
Contact: [email protected]
196
Description:
197
(RO) CXL port objects are enumerated from either a platform
198
firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
199
port with CXL component registers. The 'uport' symlink connects
200
the CXL portX object to the device that published the CXL port
201
capability.
204
What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport
205
Date: January, 2023
206
KernelVersion: v6.3
207
Contact: [email protected]
208
Description:
209
(RO) CXL port objects are instantiated for each upstream port in
210
a CXL/PCIe switch, and for each endpoint to map the
211
corresponding memory device into the CXL port hierarchy. When a
212
descendant CXL port (switch or endpoint) is enumerated it is
213
useful to know which 'dport' object in the parent CXL port
214
routes to this descendant. The 'parent_dport' symlink points to
215
the device representing the downstream port of a CXL switch that
216
routes to {port,endpoint}X.
219
What: /sys/bus/cxl/devices/portX/dportY
220
Date: June, 2021
221
KernelVersion: v5.14
222
Contact: [email protected]
223
Description:
224
(RO) CXL port objects are enumerated from either a platform
225
firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
226
port with CXL component registers. The 'dportY' symlink
227
identifies one or more downstream ports that the upstream port
228
may target in its decode of CXL memory resources. The 'Y'
229
integer reflects the hardware port unique-id used in the
230
hardware decoder target list.
233
What: /sys/bus/cxl/devices/portX/decoders_committed
234
Date: October, 2023
235
KernelVersion: v6.7
236
Contact: [email protected]
237
Description:
238
(RO) A memory device is considered active when any of its
239
decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7
240
CXL HDM Decoder n Control Register). Hotplug and destructive
241
operations like "sanitize" are blocked while device is actively
242
decoding a Host Physical Address range. Note that this number
243
may be elevated without any regionX objects active or even
244
enumerated, as this may be due to decoders established by
245
platform firmware or a previous kernel (kexec).
248
What: /sys/bus/cxl/devices/decoderX.Y
249
Date: June, 2021
250
KernelVersion: v5.14
251
Contact: [email protected]
252
Description:
253
(RO) CXL decoder objects are enumerated from either a platform
254
firmware description, or a CXL HDM decoder register set in a
255
PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
256
Capability Structure). The 'X' in decoderX.Y represents the
257
cxl_port container of this decoder, and 'Y' represents the
258
instance id of a given decoder resource.
261
What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
262
Date: June, 2021
263
KernelVersion: v5.14
264
Contact: [email protected]
265
Description:
266
(RO) The 'start' and 'size' attributes together convey the
267
physical address base and number of bytes mapped in the
268
decoder's decode window. For decoders of devtype
269
"cxl_decoder_root" the address range is fixed. For decoders of
270
devtype "cxl_decoder_switch" the address is bounded by the
271
decode range of the cxl_port ancestor of the decoder's cxl_port,
272
and dynamically updates based on the active memory regions in
273
that address space.
276
What: /sys/bus/cxl/devices/decoderX.Y/locked
277
Date: June, 2021
278
KernelVersion: v5.14
279
Contact: [email protected]
280
Description:
281
(RO) CXL HDM decoders have the capability to lock the
282
configuration until the next device reset. For decoders of
283
devtype "cxl_decoder_root" there is no standard facility to
284
unlock them. For decoders of devtype "cxl_decoder_switch" a
285
secondary bus reset, of the PCIe bridge that provides the bus
286
for this decoders uport, unlocks / resets the decoder.
289
What: /sys/bus/cxl/devices/decoderX.Y/target_list
290
Date: June, 2021
291
KernelVersion: v5.14
292
Contact: [email protected]
293
Description:
294
(RO) Display a comma separated list of the current decoder
295
target configuration. The list is ordered by the current
296
configured interleave order of the decoder's dport instances.
297
Each entry in the list is a dport id.
300
What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
301
Date: June, 2021
302
KernelVersion: v5.14
303
Contact: [email protected]
304
Description:
305
(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
306
represents a fixed memory window identified by platform
307
firmware. A fixed window may only support a subset of memory
308
types. The 'cap_*' attributes indicate whether persistent
309
memory, volatile memory, accelerator memory, and / or expander
310
memory may be mapped behind this decoder's memory window.
313
What: /sys/bus/cxl/devices/decoderX.Y/target_type
314
Date: June, 2021
315
KernelVersion: v5.14
316
Contact: [email protected]
317
Description:
318
(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
319
can optionally decode either accelerator memory (type-2) or
320
expander memory (type-3). The 'target_type' attribute indicates
321
the current setting which may dynamically change based on what
322
memory regions are activated in this decode hierarchy.
325
What: /sys/bus/cxl/devices/endpointX/CDAT
326
Date: July, 2022
327
KernelVersion: v6.0
328
Contact: [email protected]
329
Description:
330
(RO) If this sysfs entry is not present no DOE mailbox was
331
found to support CDAT data. If it is present and the length of
332
the data is 0 reading the CDAT data failed. Otherwise the CDAT
333
data is reported.
336
What: /sys/bus/cxl/devices/decoderX.Y/mode
337
Date: May, 2022
338
KernelVersion: v6.0
339
Contact: [email protected]
340
Description:
341
(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
342
translates from a host physical address range, to a device
343
local address range. Device-local address ranges are further
344
split into a 'ram' (volatile memory) range and 'pmem'
345
(persistent memory) range. The 'mode' attribute emits one of
346
'ram', 'pmem', or 'none'. The 'none' indicates the decoder is
347
not actively decoding, or no DPA allocation policy has been
348
set.
350
'mode' can be written, when the decoder is in the 'disabled'
351
state, with either 'ram' or 'pmem' to set the boundaries for the
352
next allocation.
355
What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
356
Date: May, 2022
357
KernelVersion: v6.0
358
Contact: [email protected]
359
Description:
360
(RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
361
and its 'dpa_size' attribute is non-zero, this attribute
362
indicates the device physical address (DPA) base address of the
363
allocation.
366
What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
367
Date: May, 2022
368
KernelVersion: v6.0
369
Contact: [email protected]
370
Description:
371
(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
372
translates from a host physical address range, to a device local
373
address range. The range, base address plus length in bytes, of
374
DPA allocated to this decoder is conveyed in these 2 attributes.
375
Allocations can be mutated as long as the decoder is in the
376
disabled state. A write to 'dpa_size' releases the previous DPA
377
allocation and then attempts to allocate from the free capacity
378
in the device partition referred to by 'decoderX.Y/mode'.
379
Allocate and free requests can only be performed on the highest
380
instance number disabled decoder with non-zero size. I.e.
381
allocations are enforced to occur in increasing 'decoderX.Y/id'
382
order and frees are enforced to occur in decreasing
383
'decoderX.Y/id' order.
386
What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
387
Date: May, 2022
388
KernelVersion: v6.0
389
Contact: [email protected]
390
Description:
391
(RO) The number of targets across which this decoder's host
392
physical address (HPA) memory range is interleaved. The device
393
maps every Nth block of HPA (of size ==
394
'interleave_granularity') to consecutive DPA addresses. The
395
decoder's position in the interleave is determined by the
396
device's (endpoint or switch) switch ancestry. For root
397
decoders their interleave is specified by platform firmware and
398
they only specify a downstream target order for host bridges.
401
What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
402
Date: May, 2022
403
KernelVersion: v6.0
404
Contact: [email protected]
405
Description:
406
(RO) The number of consecutive bytes of host physical address
407
space this decoder claims at address N before the decode rotates
408
to the next target in the interleave at address N +
409
interleave_granularity (assuming N is aligned to
410
interleave_granularity).
413
What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region
414
Date: May, 2022, January, 2023
415
KernelVersion: v6.0 (pmem), v6.3 (ram)
416
Contact: [email protected]
417
Description:
418
(RW) Write a string in the form 'regionZ' to start the process
419
of defining a new persistent, or volatile memory region
420
(interleave-set) within the decode range bounded by root decoder
421
'decoderX.Y'. The value written must match the current value
422
returned from reading this attribute. An atomic compare exchange
423
operation is done on write to assign the requested id to a
424
region and allocate the region-id for the next creation attempt.
425
EBUSY is returned if the region name written does not match the
426
current cached value.
429
What: /sys/bus/cxl/devices/decoderX.Y/delete_region
430
Date: May, 2022
431
KernelVersion: v6.0
432
Contact: [email protected]
433
Description:
434
(WO) Write a string in the form 'regionZ' to delete that region,
435
provided it is currently idle / not bound to a driver.
438
What: /sys/bus/cxl/devices/decoderX.Y/qos_class
439
Date: May, 2023
440
KernelVersion: v6.5
441
Contact: [email protected]
442
Description:
443
(RO) For CXL host platforms that support "QoS Telemetry" this
444
root-decoder-only attribute conveys a platform specific cookie
445
that identifies a QoS performance class for the CXL Window.
446
This class-id can be compared against a similar "qos_class"
447
published for each memory-type that an endpoint supports. While
448
it is not required that endpoints map their local memory-class
449
to a matching platform class, mismatches are not recommended and
450
there are platform specific side-effects that may result.
453
What: /sys/bus/cxl/devices/regionZ/uuid
454
Date: May, 2022
455
KernelVersion: v6.0
456
Contact: [email protected]
457
Description:
458
(RW) Write a unique identifier for the region. This field must
459
be set for persistent regions and it must not conflict with the
460
UUID of another region. For volatile ram regions this
461
attribute is a read-only empty string.
464
What: /sys/bus/cxl/devices/regionZ/interleave_granularity
465
Date: May, 2022
466
KernelVersion: v6.0
467
Contact: [email protected]
468
Description:
469
(RW) Set the number of consecutive bytes each device in the
470
interleave set will claim. The possible interleave granularity
471
values are determined by the CXL spec and the participating
472
devices.
475
What: /sys/bus/cxl/devices/regionZ/interleave_ways
476
Date: May, 2022
477
KernelVersion: v6.0
478
Contact: [email protected]
479
Description:
480
(RW) Configures the number of devices participating in the
481
region is set by writing this value. Each device will provide
482
1/interleave_ways of storage for the region.
485
What: /sys/bus/cxl/devices/regionZ/size
486
Date: May, 2022
487
KernelVersion: v6.0
488
Contact: [email protected]
489
Description:
490
(RW) System physical address space to be consumed by the region.
491
When written trigger the driver to allocate space out of the
492
parent root decoder's address space. When read the size of the
493
address space is reported and should match the span of the
494
region's resource attribute. Size shall be set after the
495
interleave configuration parameters. Once set it cannot be
496
changed, only freed by writing 0. The kernel makes no guarantees
497
that data is maintained over an address space freeing event, and
498
there is no guarantee that a free followed by an allocate
499
results in the same address being allocated.
502
What: /sys/bus/cxl/devices/regionZ/mode
503
Date: January, 2023
504
KernelVersion: v6.3
505
Contact: [email protected]
506
Description:
507
(RO) The mode of a region is established at region creation time
508
and dictates the mode of the endpoint decoder that comprise the
509
region. For more details on the possible modes see
510
/sys/bus/cxl/devices/decoderX.Y/mode
513
What: /sys/bus/cxl/devices/regionZ/resource
514
Date: May, 2022
515
KernelVersion: v6.0
516
Contact: [email protected]
517
Description:
518
(RO) A region is a contiguous partition of a CXL root decoder
519
address space. Region capacity is allocated by writing to the
520
size attribute, the resulting physical address space determined
521
by the driver is reflected here. It is therefore not useful to
522
read this before writing a value to the size attribute.
525
What: /sys/bus/cxl/devices/regionZ/target[0..N]
526
Date: May, 2022
527
KernelVersion: v6.0
528
Contact: [email protected]
529
Description:
530
(RW) Write an endpoint decoder object name to 'targetX' where X
531
is the intended position of the endpoint device in the region
532
interleave and N is the 'interleave_ways' setting for the
533
region. ENXIO is returned if the write results in an impossible
534
to map decode scenario, like the endpoint is unreachable at that
535
position relative to the root decoder interleave. EBUSY is
536
returned if the position in the region is already occupied, or
537
if the region is not in a state to accept interleave
538
configuration changes. EINVAL is returned if the object name is
539
not an endpoint decoder. Once all positions have been
540
successfully written a final validation for decode conflicts is
541
performed before activating the region.
544
What: /sys/bus/cxl/devices/regionZ/commit
545
Date: May, 2022
546
KernelVersion: v6.0
547
Contact: [email protected]
548
Description:
549
(RW) Write a boolean 'true' string value to this attribute to
550
trigger the region to transition from the software programmed
551
state to the actively decoding in hardware state. The commit
552
operation in addition to validating that the region is in proper
553
configured state, validates that the decoders are being
554
committed in spec mandated order (last committed decoder id +
555
1), and checks that the hardware accepts the commit request.
556
Reading this value indicates whether the region is committed or
557
not.
560
What: /sys/bus/cxl/devices/memX/trigger_poison_list
561
Date: April, 2023
562
KernelVersion: v6.4
563
Contact: [email protected]
564
Description:
565
(WO) When a boolean 'true' is written to this attribute the
566
memdev driver retrieves the poison list from the device. The
567
list consists of addresses that are poisoned, or would result
568
in poison if accessed, and the source of the poison. This
569
attribute is only visible for devices supporting the
570
capability. The retrieved errors are logged as kernel
571
events when cxl_poison event tracing is enabled.
574
What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth
575
/sys/bus/cxl/devices/regionZ/accessY/write_bandwidth
576
Date: Jan, 2024
577
KernelVersion: v6.9
578
Contact: [email protected]
579
Description:
580
(RO) The aggregated read or write bandwidth of the region. The
581
number is the accumulated read or write bandwidth of all CXL memory
582
devices that contributes to the region in MB/s. It is
583
identical data that should appear in
584
/sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or
585
/sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth.
586
See Documentation/ABI/stable/sysfs-devices-node. access0 provides
587
the number to the closest initiator and access1 provides the
588
number to the closest CPU.
591
What: /sys/bus/cxl/devices/regionZ/accessY/read_latency
592
/sys/bus/cxl/devices/regionZ/accessY/write_latency
593
Date: Jan, 2024
594
KernelVersion: v6.9
595
Contact: [email protected]
596
Description:
597
(RO) The read or write latency of the region. The number is
598
the worst read or write latency of all CXL memory devices that
599
contributes to the region in nanoseconds. It is identical data
600
that should appear in
601
/sys/devices/system/node/nodeX/accessY/initiators/read_latency or
602
/sys/devices/system/node/nodeX/accessY/initiators/write_latency.
603
See Documentation/ABI/stable/sysfs-devices-node. access0 provides
604
the number to the closest initiator and access1 provides the
605
number to the closest CPU.
608
What: /sys/bus/cxl/devices/nvdimm-bridge0/ndbusX/nmemY/cxl/dirty_shutdown
609
Date: Feb, 2025
610
KernelVersion: v6.15
611
Contact: [email protected]
612
Description:
613
(RO) The device dirty shutdown count value, which is the number
614
of times the device could have incurred in potential data loss.
615
The count is persistent across power loss and wraps back to 0
616
upon overflow. If this file is not present, the device does not
617
have the necessary support for dirty tracking.
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
CXL bus unbind flush
1-8| 항목 | 전문 번역 |
|---|---|
| What | /sys/bus/cxl/flush |
| Date | 2022년 1월 |
| KernelVersion | v5.18 |
| Contact | [email protected] |
| Description | (WO) Userspace가 port를 수동으로 unbind하면 kernel은 모든 descendant memdevs를 unbind하도록 예약합니다. 이 attribute에 1을 쓰면 해당 work를 flush합니다. |
CXL memdev identity, capacity와 QoS
11-110| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/memX/firmware_version | 2020년 12월 / v5.12 / [email protected] | (RO) CXL-2.0 specification의 Identify Memory Device Output Payload가 보고하는 "FW Revision" 문자열입니다. |
| /sys/bus/cxl/devices/memX/payload_max | 2020년 12월 / v5.12 / [email protected] | (RO) Mailbox command payload registers의 최대 크기(bytes)입니다. Device가 더 큰 크기를 보고하면 Linux는 이를 1MB로 제한합니다. |
| /sys/bus/cxl/devices/memX/label_storage_size | 2021년 5월 / v5.13 / [email protected] | (RO) Label Storage Area(LSA)의 크기(bytes)입니다. |
| /sys/bus/cxl/devices/memX/ram/size | 2020년 12월 / v5.12 / [email protected] | (RO) "Volatile Only Capacity"를 bytes로 나타냅니다. CXL-2.0 specification의 Identify Memory Device Output Payload에 있는 같은 이름의 field를 나타냅니다. |
| /sys/bus/cxl/devices/memX/ram/qos_class | 2023년 5월 / v6.8 / [email protected] | (RO) "QoS Telemetry"를 지원하는 CXL host platform에서 CXL mem device volatile partition의 QoS performance class를 식별하는 platform-specific cookies의 comma-delimited list입니다. Root decoder가 게시하는 qos_class와 class-ids를 비교할 수 있습니다. Endpoints의 local memory-class가 matching platform class에 반드시 map될 필요는 없지만 mismatch는 권장되지 않으며 platform-specific performance side-effects가 생길 수 있습니다. 첫 번째 class-id가 표시됩니다. |
| /sys/bus/cxl/devices/memX/pmem/size | 2020년 12월 / v5.12 / [email protected] | (RO) "Persistent Only Capacity"를 bytes로 나타냅니다. CXL-2.0 specification의 Identify Memory Device Output Payload에 있는 같은 이름의 field를 나타냅니다. |
| /sys/bus/cxl/devices/memX/pmem/qos_class | 2023년 5월 / v6.8 / [email protected] | (RO) "QoS Telemetry"를 지원하는 CXL host platform에서 CXL mem device persistent partition의 QoS performance class를 식별하는 platform-specific cookies의 comma-delimited list입니다. Root decoder가 게시하는 qos_class와 class-ids를 비교할 수 있습니다. Endpoints의 local memory-class가 matching platform class에 반드시 map될 필요는 없지만 mismatch는 권장되지 않으며 platform-specific performance side-effects가 생길 수 있습니다. 첫 번째 class-id가 표시됩니다. |
| /sys/bus/cxl/devices/memX/serial | 2022년 1월 / v5.18 / [email protected] | (RO) PCIe Device Serial Number capability에 따른 64-bit serial number입니다. CXL devices에 필수이며 CXL 2.0 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities를 참조합니다. |
| /sys/bus/cxl/devices/memX/numa_node | 2022년 1월 / v5.18 / [email protected] | (RO) NUMA가 enable되어 있고 platform이 이 memory device의 host PCI device에 affinity를 부여했다면 이 device의 CPU node affinity를 출력합니다. |
CXL memdev security와 firmware
113-169| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/memX/security/state | 2023년 6월 / v6.5 / [email protected] | (RO) 이 file을 읽으면 device의 CXL security state를 표시합니다. 가능한 states는 disabled, sanitization 진행 중인 sanitize, 그리고 persistent memory에만 가능한 locked, unlocked, frozen입니다. Userspace는 sanitize operation 완료 알림을 받기 위해 이 sysfs entry에 select/poll을 사용할 수 있습니다. |
| /sys/bus/cxl/devices/memX/security/sanitize | 2023년 6월 / v6.5 / [email protected] | (WO) 이 attribute에 boolean 문자열 true를 쓰면 device를 안전하게 재사용하거나 폐기하도록 sanitize합니다. Persistent capacity, volatile capacity 또는 LSA에 있는 모든 user data와 metadata를 media type에 적합한 수단으로 영구적으로 사용할 수 없게 합니다. Device가 disable되어 어떤 HPA range도 active decoding하지 않아야 합니다. 따라서 explicit global CPU cache management를 피하고 region이 software-programmed state와 hardware-committed state 사이를 전환할 때 cache management가 이루어지도록 맡길 수 있습니다. File이 없으면 이 operation을 hardware가 지원하지 않습니다. |
| /sys/bus/cxl/devices/memX/security/erase | 2023년 6월 / v6.5 / [email protected] | (WO) 이 attribute에 boolean 문자열 true를 쓰면 device의 모든 user data areas에 대한 media encryption keys를 변경해 user data를 secure erase합니다. Device가 disable되어 어떤 HPA range도 active decoding하지 않아야 합니다. 따라서 explicit global CPU cache management를 피하고 region이 software-programmed state와 hardware-committed state 사이를 전환할 때 cache management가 이루어지도록 맡길 수 있습니다. File이 없으면 이 operation을 hardware가 지원하지 않습니다. |
| /sys/bus/cxl/devices/memX/firmware/ | 2023년 4월 / v6.5 / [email protected] | (RW) Firmware uploader mechanism입니다. 이 directory 아래의 files로 CXL devices용 새 firmware를 upload하고 activate할 수 있습니다. 이 interfaces는 sysfs-class-firmware에 문서화되어 있습니다. |
Region hardware committed→Decommit region→Device disabled→Write true to sanitize→All user data and metadata unavailable
Region hardware committed→Decommit region→Device disabled→Write true to erase→Media encryption keys changed
두 destructive security operations 모두 device가 HPA ranges를 decoding하지 않는 disabled state여야 합니다.
CXL device identity와 port hierarchy
172-245| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/*/devtype | 2021년 6월 / v5.14 / [email protected] | (RO) CXL device objects는 cxl bus devices의 uevents에서 DEVTYPE environment variable로 전달되는 값과 같은 값을 반영하는 devtype attribute를 export합니다. |
| /sys/bus/cxl/devices/*/modalias | 2021년 12월 / v5.18 / [email protected] | (RO) CXL device objects는 cxl bus devices의 uevents에서 MODALIAS environment variable로 전달되는 값과 같은 값을 반영하는 modalias attribute를 export합니다. |
| /sys/bus/cxl/devices/portX/uport | 2021년 6월 / v5.14 / [email protected] | (RO) CXL port objects는 platform firmware device(ACPI0017, ACPI0016) 또는 CXL component registers가 있는 PCIe switch upstream port에서 enumerate됩니다. uport symlink는 CXL portX object를 CXL port capability를 게시한 device와 연결합니다. |
| /sys/bus/cxl/devices/{port,endpoint}X/parent_dport | 2023년 1월 / v6.3 / [email protected] | (RO) CXL port objects는 CXL/PCIe switch의 각 upstream port와 corresponding memory device를 CXL port hierarchy에 map하는 각 endpoint에 대해 instantiate됩니다. Descendant CXL port가 enumerate될 때 parent CXL port의 어느 dport object가 해당 descendant로 route하는지 알려 줍니다. parent_dport symlink는 {port,endpoint}X로 route하는 CXL switch downstream port를 나타내는 device를 가리킵니다. |
| /sys/bus/cxl/devices/portX/dportY | 2021년 6월 / v5.14 / [email protected] | (RO) dportY symlink는 upstream port가 CXL memory resources를 decode할 때 target으로 삼을 수 있는 하나 이상의 downstream ports를 식별합니다. Y integer는 hardware decoder target list에서 사용하는 hardware port unique-id입니다. |
| /sys/bus/cxl/devices/portX/decoders_committed | 2023년 10월 / v6.7 / [email protected] | (RO) Memory device의 decoder 중 하나라도 committed state이면 device를 active로 간주합니다(CXL 3.0 8.2.4.19.7 CXL HDM Decoder n Control Register 참조). Device가 HPA range를 active decoding하는 동안 hotplug와 sanitize 같은 destructive operations를 차단합니다. Platform firmware나 이전 kernel(kexec)이 만든 decoders 때문에 active 또는 enumerate된 regionX objects가 없어도 이 수가 증가할 수 있습니다. |
Platform firmware or PCIe upstream port→uport→CXL portX→dportY→Descendant port or endpoint
Descendant port or endpoint→parent_dport→Parent CXL switch downstream port
uport는 capability publisher를, dport와 parent_dport는 parent에서 descendant로 향하는 routing 관계를 나타냅니다.
CXL decoder windows와 capabilities
248-333| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/decoderX.Y | 2021년 6월 / v5.14 / [email protected] | (RO) CXL decoder objects는 platform firmware description 또는 PCIe device의 CXL HDM decoder register set에서 enumerate됩니다(CXL 2.0 section 8.2.5.12 CXL HDM Decoder Capability Structure 참조). decoderX.Y의 X는 decoder를 담는 cxl_port를, Y는 해당 decoder resource의 instance id를 나타냅니다. |
| /sys/bus/cxl/devices/decoderX.Y/{start,size} | 2021년 6월 / v5.14 / [email protected] | (RO) start와 size는 decoder decode window의 physical address base와 mapping된 bytes 수를 함께 나타냅니다. cxl_decoder_root는 address range가 고정됩니다. cxl_decoder_switch는 decoder cxl_port의 cxl_port ancestor decode range에 의해 address가 제한되고 해당 address space의 active memory regions에 따라 동적으로 갱신됩니다. |
| /sys/bus/cxl/devices/decoderX.Y/locked | 2021년 6월 / v5.14 / [email protected] | (RO) CXL HDM decoders는 다음 device reset까지 configuration을 lock할 수 있습니다. cxl_decoder_root에는 표준 unlock 수단이 없습니다. cxl_decoder_switch는 decoder uport의 bus를 제공하는 PCIe bridge에 secondary bus reset을 수행하면 decoder를 unlock/reset합니다. |
| /sys/bus/cxl/devices/decoderX.Y/target_list | 2021년 6월 / v5.14 / [email protected] | (RO) 현재 decoder target configuration을 comma-separated list로 표시합니다. List는 decoder dport instances의 현재 configured interleave order로 정렬되며 각 entry는 dport id입니다. |
| /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} | 2021년 6월 / v5.14 / [email protected] | (RO) cxl_decoder_root decoder는 platform firmware가 식별한 fixed memory window이며 일부 memory types만 지원할 수 있습니다. cap_* attributes는 persistent memory, volatile memory, accelerator memory 및 expander memory를 이 decoder memory window 뒤에 map할 수 있는지 나타냅니다. |
| /sys/bus/cxl/devices/decoderX.Y/target_type | 2021년 6월 / v5.14 / [email protected] | (RO) cxl_decoder_switch decoder는 accelerator memory(type-2) 또는 expander memory(type-3)를 선택적으로 decode할 수 있습니다. target_type은 현재 설정을 나타내며 decode hierarchy에서 활성화된 memory regions에 따라 동적으로 바뀔 수 있습니다. |
| /sys/bus/cxl/devices/endpointX/CDAT | 2022년 7월 / v6.0 / [email protected] | (RO) 이 sysfs entry가 없으면 CDAT data를 지원하는 DOE mailbox를 찾지 못한 것입니다. Entry가 있고 data length가 0이면 CDAT data 읽기에 실패한 것이며, 그 외에는 CDAT data가 보고됩니다. |
Endpoint decoder mode, DPA와 interleave
336-410| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/decoderX.Y/mode | 2022년 5월 / v6.0 / [email protected] | (RW) cxl_decoder_endpoint decoder는 host physical address range를 device-local address range로 translate합니다. Device-local ranges는 ram(volatile memory)과 pmem(persistent memory)으로 나뉩니다. mode는 ram, pmem 또는 none을 출력하며 none은 decoder가 active decoding하지 않거나 DPA allocation policy가 설정되지 않았음을 뜻합니다. Decoder가 disabled state일 때 ram 또는 pmem을 써서 다음 allocation의 boundaries를 정할 수 있습니다. |
| /sys/bus/cxl/devices/decoderX.Y/dpa_resource | 2022년 5월 / v6.0 / [email protected] | (RO) cxl_decoder_endpoint decoder에서 dpa_size가 0이 아니면 allocation의 device physical address(DPA) base address를 나타냅니다. |
| /sys/bus/cxl/devices/decoderX.Y/dpa_size | 2022년 5월 / v6.0 / [email protected] | (RW) cxl_decoder_endpoint가 HPA range를 device-local range로 translate할 때 decoder에 할당된 DPA range의 base address와 length(bytes)는 dpa_resource와 dpa_size 두 attributes로 나타냅니다. Decoder가 disabled state이면 allocation을 변경할 수 있습니다. dpa_size에 쓰면 이전 allocation을 release하고 decoderX.Y/mode가 가리키는 device partition의 free capacity에서 새로 allocate합니다. Allocate/free requests는 non-zero size를 가진 disabled decoder 중 가장 높은 instance number에서만 수행할 수 있습니다. 따라서 allocation은 decoderX.Y/id 증가 순서, free는 감소 순서를 강제합니다. |
| /sys/bus/cxl/devices/decoderX.Y/interleave_ways | 2022년 5월 / v6.0 / [email protected] | (RO) 이 decoder의 HPA memory range가 interleave되는 targets 수입니다. Device는 interleave_granularity 크기의 HPA N번째 block마다 consecutive DPA addresses에 map합니다. Interleave에서 decoder 위치는 endpoint 또는 switch의 switch ancestry로 결정됩니다. Root decoders의 interleave는 platform firmware가 지정하며 host bridges에 대한 downstream target order만 지정합니다. |
| /sys/bus/cxl/devices/decoderX.Y/interleave_granularity | 2022년 5월 / v6.0 / [email protected] | (RO) N이 interleave_granularity에 align되어 있다고 할 때, decode가 N + interleave_granularity의 다음 target으로 rotate하기 전에 이 decoder가 address N에서 차지하는 consecutive HPA bytes 수입니다. |
Root decoder region lifecycle와 QoS
413-450| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region | 2022년 5월, 2023년 1월 / v6.0(pmem), v6.3(ram) / [email protected] | (RW) regionZ 형식 문자열을 써서 root decoder decoderX.Y가 제한하는 decode range 안에 새 persistent 또는 volatile memory region(interleave-set)을 정의하는 과정을 시작합니다. 쓴 값은 이 attribute를 읽어 반환된 현재 값과 일치해야 합니다. Write 시 atomic compare-exchange로 요청한 id를 region에 할당하고 다음 생성 시도를 위한 region-id를 allocate합니다. 쓴 region name이 cached current value와 일치하지 않으면 EBUSY를 반환합니다. |
| /sys/bus/cxl/devices/decoderX.Y/delete_region | 2022년 5월 / v6.0 / [email protected] | (WO) regionZ 형식 문자열을 쓰면 해당 region이 현재 idle 상태이고 driver에 bind되지 않은 경우 삭제합니다. |
| /sys/bus/cxl/devices/decoderX.Y/qos_class | 2023년 5월 / v6.5 / [email protected] | (RO) QoS Telemetry를 지원하는 CXL host platform에서 root-decoder 전용인 이 attribute는 CXL Window의 QoS performance class를 식별하는 platform-specific cookie를 전달합니다. Endpoint가 지원하는 각 memory type의 qos_class와 비교할 수 있습니다. Endpoint local memory-class가 matching platform class에 반드시 map될 필요는 없지만 mismatch는 권장되지 않으며 platform-specific side-effects가 생길 수 있습니다. |
CXL region configuration과 hardware commit
453-557| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/regionZ/uuid | 2022년 5월 / v6.0 / [email protected] | (RW) Region의 unique identifier를 씁니다. Persistent regions에서는 이 field를 설정해야 하며 다른 region UUID와 충돌하면 안 됩니다. Volatile ram regions에서는 read-only empty string입니다. |
| /sys/bus/cxl/devices/regionZ/interleave_granularity | 2022년 5월 / v6.0 / [email protected] | (RW) Interleave set의 각 device가 차지할 consecutive bytes 수를 설정합니다. 가능한 interleave granularity values는 CXL spec과 참여 devices가 결정합니다. |
| /sys/bus/cxl/devices/regionZ/interleave_ways | 2022년 5월 / v6.0 / [email protected] | (RW) 이 값을 써서 region에 참여하는 devices 수를 구성합니다. 각 device는 region storage의 1/interleave_ways를 제공합니다. |
| /sys/bus/cxl/devices/regionZ/size | 2022년 5월 / v6.0 / [email protected] | (RW) Region이 사용할 system physical address space입니다. 값을 쓰면 parent root decoder address space에서 공간을 allocate하며 읽으면 address-space size를 보고합니다. 이는 region resource attribute span과 일치해야 합니다. Interleave parameters를 설정한 뒤 size를 설정해야 합니다. 한번 설정하면 변경할 수 없고 0을 써서 free만 할 수 있습니다. Kernel은 address-space free 중 data 유지나 free 후 재allocate 시 같은 address 재할당을 보장하지 않습니다. |
| /sys/bus/cxl/devices/regionZ/mode | 2023년 1월 / v6.3 / [email protected] | (RO) Region mode는 region 생성 시 정해지며 region을 구성하는 endpoint decoders의 mode를 결정합니다. 가능한 modes는 /sys/bus/cxl/devices/decoderX.Y/mode를 참조합니다. |
| /sys/bus/cxl/devices/regionZ/resource | 2022년 5월 / v6.0 / [email protected] | (RO) Region은 CXL root decoder address space의 contiguous partition입니다. size에 써서 capacity를 allocate하면 driver가 정한 resulting physical address space가 여기에 반영됩니다. 따라서 size에 값을 쓰기 전에는 읽어도 유용하지 않습니다. |
| /sys/bus/cxl/devices/regionZ/target[0..N] | 2022년 5월 / v6.0 / [email protected] | (RW) Endpoint device가 region interleave에서 차지할 position X의 targetX에 endpoint decoder object name을 씁니다. N은 region interleave_ways 설정입니다. Root decoder interleave 기준 해당 position에서 endpoint에 도달할 수 없는 등 impossible-to-map decode scenario이면 ENXIO, position이 이미 점유되었거나 region이 interleave 변경을 받을 상태가 아니면 EBUSY, object name이 endpoint decoder가 아니면 EINVAL을 반환합니다. 모든 positions에 성공적으로 쓴 뒤 region 활성화 전에 decode conflicts를 최종 검증합니다. |
| /sys/bus/cxl/devices/regionZ/commit | 2022년 5월 / v6.0 / [email protected] | (RW) Boolean 문자열 true를 쓰면 region을 software-programmed state에서 hardware가 active decoding하는 state로 전환합니다. Commit은 region configuration이 올바른지 확인하고 decoders가 spec-mandated order(last committed decoder id + 1)로 commit되는지 검증하며 hardware가 요청을 수락하는지 확인합니다. 읽으면 region commit 여부를 나타냅니다. |
create_pmem_region or create_ram_region→Set uuid when persistent→Set interleave granularity and ways→Set size→Assign target[0..N]→Write true to commit→Hardware active decoding
Committed region→Decommit→Write 0 to size→Idle and unbound→delete_region
Region ID를 만든 뒤 interleave와 address space, endpoint positions를 구성하고 마지막에 hardware commit합니다.
CXL poison, performance와 dirty shutdown
560-617| What | Date / Kernel / Contact | 전문 번역 |
|---|---|---|
| /sys/bus/cxl/devices/memX/trigger_poison_list | 2023년 4월 / v6.4 / [email protected] | (WO) Boolean true를 쓰면 memdev driver가 device에서 poison list를 가져옵니다. List에는 poisoned addresses 또는 access하면 poison이 발생할 addresses와 poison source가 포함됩니다. Capability를 지원하는 devices에만 이 attribute가 보입니다. cxl_poison event tracing이 enable되어 있으면 가져온 errors를 kernel events로 기록합니다. |
| /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth /sys/bus/cxl/devices/regionZ/accessY/write_bandwidth | 2024년 1월 / v6.9 / [email protected] | (RO) Region의 aggregate read 또는 write bandwidth입니다. Region에 기여하는 모든 CXL memory devices의 누적 bandwidth를 MB/s로 나타냅니다. /sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth 또는 write_bandwidth에 나타나는 data와 같습니다. Documentation/ABI/stable/sysfs-devices-node를 참조합니다. access0은 가장 가까운 initiator, access1은 가장 가까운 CPU에 대한 값을 제공합니다. |
| /sys/bus/cxl/devices/regionZ/accessY/read_latency /sys/bus/cxl/devices/regionZ/accessY/write_latency | 2024년 1월 / v6.9 / [email protected] | (RO) Region의 read 또는 write latency입니다. Region에 기여하는 모든 CXL memory devices 중 최악의 latency를 nanoseconds로 나타냅니다. /sys/devices/system/node/nodeX/accessY/initiators/read_latency 또는 write_latency에 나타나는 data와 같습니다. Documentation/ABI/stable/sysfs-devices-node를 참조합니다. access0은 가장 가까운 initiator, access1은 가장 가까운 CPU에 대한 값을 제공합니다. |
| /sys/bus/cxl/devices/nvdimm-bridge0/ndbusX/nmemY/cxl/dirty_shutdown | 2025년 2월 / v6.15 / [email protected] | (RO) Device가 potential data loss를 겪었을 수 있는 횟수인 dirty shutdown count입니다. Count는 power loss 뒤에도 유지되고 overflow하면 0으로 wrap합니다. 이 file이 없으면 device에 dirty tracking 지원이 없습니다. |
Descendant memdev unbind flush
sysfs-bus-cxl:1-8flush는 userspace가 port를 수동 unbind한 뒤 kernel이 예약한 descendant memdev unbind work를 즉시 flush합니다.