요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
1
.. SPDX-License-Identifier: GPL-2.0
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=================
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PCI Test Function
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=================
7
:Author: Kishon Vijay Abraham I <[email protected]>
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Traditionally PCI RC has always been validated by using standard
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PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
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However with the addition of EP-core in linux kernel, it is possible
12
to configure a PCI controller that can operate in EP mode to work as
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a test device.
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The PCI endpoint test device is a virtual device (defined in software)
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used to test the endpoint functionality and serve as a sample driver
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for other PCI endpoint devices (to use the EP framework).
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The PCI endpoint test device has the following registers:
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1) PCI_ENDPOINT_TEST_MAGIC
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2) PCI_ENDPOINT_TEST_COMMAND
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3) PCI_ENDPOINT_TEST_STATUS
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4) PCI_ENDPOINT_TEST_SRC_ADDR
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5) PCI_ENDPOINT_TEST_DST_ADDR
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6) PCI_ENDPOINT_TEST_SIZE
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7) PCI_ENDPOINT_TEST_CHECKSUM
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8) PCI_ENDPOINT_TEST_IRQ_TYPE
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9) PCI_ENDPOINT_TEST_IRQ_NUMBER
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* PCI_ENDPOINT_TEST_MAGIC
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This register will be used to test BAR0. A known pattern will be written
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and read back from MAGIC register to verify BAR0.
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* PCI_ENDPOINT_TEST_COMMAND
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This register will be used by the host driver to indicate the function
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that the endpoint device must perform.
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======== ================================================================
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Bitfield Description
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======== ================================================================
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Bit 0 raise legacy IRQ
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Bit 1 raise MSI IRQ
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Bit 2 raise MSI-X IRQ
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Bit 3 read command (read data from RC buffer)
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Bit 4 write command (write data to RC buffer)
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Bit 5 copy command (copy data from one RC buffer to another RC buffer)
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======== ================================================================
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* PCI_ENDPOINT_TEST_STATUS
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This register reflects the status of the PCI endpoint device.
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======== ==============================
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Bitfield Description
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======== ==============================
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Bit 0 read success
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Bit 1 read fail
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Bit 2 write success
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Bit 3 write fail
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Bit 4 copy success
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Bit 5 copy fail
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Bit 6 IRQ raised
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Bit 7 source address is invalid
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Bit 8 destination address is invalid
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======== ==============================
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* PCI_ENDPOINT_TEST_SRC_ADDR
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This register contains the source address (RC buffer address) for the
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COPY/READ command.
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* PCI_ENDPOINT_TEST_DST_ADDR
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This register contains the destination address (RC buffer address) for
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the COPY/WRITE command.
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* PCI_ENDPOINT_TEST_IRQ_TYPE
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This register contains the interrupt type (Legacy/MSI) triggered
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for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
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Possible types:
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====== ==
88
Legacy 0
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MSI 1
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MSI-X 2
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====== ==
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* PCI_ENDPOINT_TEST_IRQ_NUMBER
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This register contains the triggered ID interrupt.
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Admissible values:
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====== ===========
100
Legacy 0
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MSI [1 .. 32]
102
MSI-X [1 .. 2048]
103
====== ===========
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
Software test endpoint
1-18저자는 Kishon Vijay Abraham I입니다. 전통적으로 PCI Root Complex는 Ethernet·USB·SATA 같은 표준 PCI card로 검증했습니다.
Linux kernel에 EP-core가 추가되면서 Endpoint mode를 지원하는 PCI controller를 test device로 구성할 수 있습니다.
PCI endpoint test device는 endpoint 기능을 시험하는 software-defined virtual device이며, EP framework를 사용하는 다른 endpoint device를 위한 sample driver이기도 합니다.
.. SPDX-License-Identifier: GPL-2.0
=================
PCI Test Function
=================
:Author: Kishon Vijay Abraham I <[email protected]>
Traditionally PCI RC has always been validated by using standard
PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
However with the addition of EP-core in linux kernel, it is possible
to configure a PCI controller that can operate in EP mode to work as
a test device.
The PCI endpoint test device is a virtual device (defined in software)
used to test the endpoint functionality and serve as a sample driver
for other PCI endpoint devices (to use the EP framework).
Register 집합과 BAR0 magic
19-35Register역할
PCI_ENDPOINT_TEST_MAGICKnown pattern write/read로 BAR0 검증
PCI_ENDPOINT_TEST_COMMANDEndpoint가 수행할 function 지시
PCI_ENDPOINT_TEST_STATUSEndpoint 처리 결과
PCI_ENDPOINT_TEST_SRC_ADDRCOPY/READ source RC buffer address
PCI_ENDPOINT_TEST_DST_ADDRCOPY/WRITE destination RC buffer address
PCI_ENDPOINT_TEST_SIZETransfer 크기
PCI_ENDPOINT_TEST_CHECKSUMData checksum
PCI_ENDPOINT_TEST_IRQ_TYPELegacy/MSI/MSI-X type
PCI_ENDPOINT_TEST_IRQ_NUMBER발생시킬 interrupt ID
Host와 endpoint가 시험 command·address·result를 교환하는 register입니다.
`PCI_ENDPOINT_TEST_MAGIC`에는 known pattern을 썼다가 다시 읽어 BAR0 접근을 검증합니다.
The PCI endpoint test device has the following registers:
1) PCI_ENDPOINT_TEST_MAGIC
2) PCI_ENDPOINT_TEST_COMMAND
3) PCI_ENDPOINT_TEST_STATUS
4) PCI_ENDPOINT_TEST_SRC_ADDR
5) PCI_ENDPOINT_TEST_DST_ADDR
6) PCI_ENDPOINT_TEST_SIZE
7) PCI_ENDPOINT_TEST_CHECKSUM
8) PCI_ENDPOINT_TEST_IRQ_TYPE
9) PCI_ENDPOINT_TEST_IRQ_NUMBER
* PCI_ENDPOINT_TEST_MAGIC
This register will be used to test BAR0. A known pattern will be written
and read back from MAGIC register to verify BAR0.
COMMAND bitfield
36-51Host driver는 `PCI_ENDPOINT_TEST_COMMAND` bit를 설정해 endpoint가 수행할 동작을 지시합니다.
Bit명령
0Legacy IRQ 발생
1MSI IRQ 발생
2MSI-X IRQ 발생
3READ: RC buffer에서 data 읽기
4WRITE: RC buffer에 data 쓰기
5COPY: 한 RC buffer에서 다른 RC buffer로 복사
Interrupt와 data transfer test operation입니다.
* PCI_ENDPOINT_TEST_COMMAND
This register will be used by the host driver to indicate the function
that the endpoint device must perform.
======== ================================================================
Bitfield Description
======== ================================================================
Bit 0 raise legacy IRQ
Bit 1 raise MSI IRQ
Bit 2 raise MSI-X IRQ
Bit 3 read command (read data from RC buffer)
Bit 4 write command (write data to RC buffer)
Bit 5 copy command (copy data from one RC buffer to another RC buffer)
======== ================================================================
STATUS bitfield
52-69`PCI_ENDPOINT_TEST_STATUS`는 endpoint device의 command 결과와 address validation 상태를 반영합니다.
Bit상태
0Read success
1Read fail
2Write success
3Write fail
4Copy success
5Copy fail
6IRQ raised
7Source address invalid
8Destination address invalid
Data command와 IRQ 결과입니다.
* PCI_ENDPOINT_TEST_STATUS
This register reflects the status of the PCI endpoint device.
======== ==============================
Bitfield Description
======== ==============================
Bit 0 read success
Bit 1 read fail
Bit 2 write success
Bit 3 write fail
Bit 4 copy success
Bit 5 copy fail
Bit 6 IRQ raised
Bit 7 source address is invalid
Bit 8 destination address is invalid
======== ==============================
Address와 IRQ register
70-103`PCI_ENDPOINT_TEST_SRC_ADDR`는 COPY/READ command의 source RC buffer address이고, `PCI_ENDPOINT_TEST_DST_ADDR`는 COPY/WRITE command의 destination RC buffer address입니다.
`PCI_ENDPOINT_TEST_IRQ_TYPE`은 READ/WRITE/COPY 또는 explicit IRQ command가 발생시킬 interrupt type을 보관합니다.
Type값
Legacy0
MSI1
MSI-X2
IRQ_TYPE register의 값입니다.
`PCI_ENDPOINT_TEST_IRQ_NUMBER`에는 발생시킬 interrupt ID를 넣습니다.
Type범위
Legacy0
MSI1..32
MSI-X1..2048
Interrupt type별 허용 ID입니다.
* PCI_ENDPOINT_TEST_SRC_ADDR
This register contains the source address (RC buffer address) for the
COPY/READ command.
* PCI_ENDPOINT_TEST_DST_ADDR
This register contains the destination address (RC buffer address) for
the COPY/WRITE command.
* PCI_ENDPOINT_TEST_IRQ_TYPE
This register contains the interrupt type (Legacy/MSI) triggered
for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
Possible types:
====== ==
Legacy 0
MSI 1
MSI-X 2
====== ==
* PCI_ENDPOINT_TEST_IRQ_NUMBER
This register contains the triggered ID interrupt.
Admissible values:
====== ===========
Legacy 0
MSI [1 .. 32]
MSI-X [1 .. 2048]
====== ===========
요약·해설
pci-test-function.rst:1-103Host가 register bit로 BAR, Legacy/MSI/MSI-X, RC buffer read·write·copy를 요청하고 endpoint가 status bit와 checksum으로 결과를 반환하는 sample function입니다.