BL33 선택과 Non-secure world 진입

QUESTION

BL33 선택과 Non-secure world 진입 단계에서 실제로 바뀌는 상태는 무엇인가?

STRUCTURE

객체와 주소가 놓이는 구조

CALL PATH

실행 흐름

STATE LEDGER

단계별 입력과 출력

호출 순서를 함수 이름으로만 외우지 않고, 각 단계가 무엇을 받아 무엇을 공개하는지 적은 표다. 실제 소스에서 생산 필드가 다르면 표를 고치는 방식으로 사용한다.

분석 범위의 전제와 비교해, 다음 단계의 입력 조건을 처음 어긴 생산 단계부터 조사한다.

VISUAL WALKTHROUGH

주소와 객체의 이동을 그림으로 읽기

아래 그림은 호출 이름보다 주소, 객체 수명과 handoff 경계를 먼저 볼 수 있도록 구성했다. 실제 주소와 크기는 사용 중인 보드의 bdinfo, map과 linker symbol을 대입한다.

UPSTREAM SOURCE

원본 코드

아래 코드는 Trusted Firmware-A LTS 2.14.3의 bl31/bl31_main.c에서 271-354줄을 그대로 가져온 것이다. 설명을 위해 실제 코드를 가짜 의사 코드로 바꾸지 않았다.

271
272/*******************************************************************************
273 * Accessor functions to help runtime services decide which image should be
274 * executed after BL31. This is BL33 or the non-secure bootloader image by
275 * default but the Secure payload dispatcher could override this by requesting
276 * an entry into BL32 (Secure payload) first. If it does so then it should use
277 * the same API to program an entry into BL33 once BL32 initialisation is
278 * complete.
279 ******************************************************************************/
280void bl31_set_next_image_type(uint32_t security_state)
281{
282	assert(sec_state_is_valid(security_state));
283	next_image_type = security_state;
284}
285
286static uint32_t bl31_get_next_image_type(void)
287{
288	return next_image_type;
289}
290
291/*******************************************************************************
292 * This function programs EL3 registers and performs other setup to enable entry
293 * into the next image after BL31 at the next ERET.
294 ******************************************************************************/
295void __init bl31_prepare_next_image_entry(void)
296{
297	const entry_point_info_t *next_image_info;
298	uint32_t image_type;
299
300#if CTX_INCLUDE_AARCH32_REGS
301	/*
302	 * Ensure that the build flag to save AArch32 system registers in CPU
303	 * context is not set for AArch64-only platforms.
304	 */
305	if (el_implemented(1) == EL_IMPL_A64ONLY) {
306		ERROR("EL1 supports AArch64-only. Please set build flag "
307				"CTX_INCLUDE_AARCH32_REGS = 0\n");
308		panic();
309	}
310#endif
311
312	/* Determine which image to execute next */
313	image_type = bl31_get_next_image_type();
314
315	/* Program EL3 registers to enable entry into the next EL */
316	next_image_info = bl31_plat_get_next_image_ep_info(image_type);
317	assert(next_image_info != NULL);
318	assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
319
320	INFO("BL31: Preparing for EL3 exit to %s world\n",
321		(image_type == SECURE) ? "secure" : "normal");
322	print_entry_point_info(next_image_info);
323	cm_init_my_context(next_image_info);
324
325	/*
326	* If we are entering the Non-secure world, use
327	* 'cm_prepare_el3_exit_ns' to exit.
328	*/
329	if (image_type == NON_SECURE) {
330		cm_prepare_el3_exit_ns();
331	} else {
332		cm_prepare_el3_exit(image_type);
333	}
334}
335
336/*******************************************************************************
337 * This function initializes the pointer to BL32 init function. This is expected
338 * to be called by the SPD after it finishes all its initialization
339 ******************************************************************************/
340void bl31_register_bl32_init(int32_t (*func)(void))
341{
342	bl32_init = func;
343}
344
345#if ENABLE_RME
346/*******************************************************************************
347 * This function initializes the pointer to RMM init function. This is expected
348 * to be called by the RMMD after it finishes all its initialization
349 ******************************************************************************/
350void bl31_register_rmm_init(int32_t (*func)(void))
351{
352	rmm_init = func;
353}
354#endif

READING CONTRACT

발췌 범위와 읽기 기준

원문 271-354줄에는 앞뒤 문맥이 포함됩니다. 기준 구문 void __init bl31_prepare_next_image_entry(void)은 L295에 있습니다. 발췌 첫 줄을 함수 정의의 시작으로 해석하지 않습니다.

BL33가 U-Boot인지 Linux인지보다 architecture handoff 계약이 중요하다. target EL, endianness, MMU/cache 상태와 x0-x3 의미를 구분한다.

RELATED SOURCE

함께 읽어야 하는 원본 코드

첫 코드 조각만으로 동작이 완성되지 않는 경우 호출 매크로, 객체 정의와 실제 실행 목록을 같은 페이지에 묶었다. 각 조각은 같은 기준 commit에서 가져왔다.

1705	}
1706}
1707#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
1708
1709/*******************************************************************************
1710 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
1711 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
1712 * updating EL1 and EL2 registers. Otherwise, it calls the generic
1713 * cm_prepare_el3_exit function.
1714 ******************************************************************************/
1715void cm_prepare_el3_exit_ns(void)
1716{
1717#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
1718#if ENABLE_ASSERTIONS
1719	cpu_context_t *ctx = cm_get_context(NON_SECURE);
1720	assert(ctx != NULL);
1721
1722	/* Assert that EL2 is used. */
1723	u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
1724	assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
1725			(el_implemented(2U) != EL_IMPL_NONE));
1726#endif /* ENABLE_ASSERTIONS */
1727
1728	/* Restore EL2 sysreg contexts */
1729	cm_el2_sysregs_context_restore(NON_SECURE);
1730	cm_set_next_eret_context(NON_SECURE);
1731#else
1732	cm_prepare_el3_exit(NON_SECURE);
1733#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
1734}
1735
1736#if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)))
1737/*******************************************************************************
1738 * The next set of six functions are used by runtime services to save and restore
1739 * EL1 context on the 'cpu_context' structure for the specified security state.
1740 ******************************************************************************/
1741static void el1_sysregs_context_save(el1_sysregs_t *ctx)
1742{
1743	write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1());
1744	write_el1_ctx_common(ctx, elr_el1, read_elr_el1());
1745
1746#if (!ERRATA_SPECULATIVE_AT)
1747	write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1());
1748	write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1());
1749#endif /* (!ERRATA_SPECULATIVE_AT) */
1750
1751	write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1());
1752	write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1());
1753	write_el1_ctx_common(ctx, sp_el1, read_sp_el1());
1754	write_el1_ctx_common(ctx, esr_el1, read_esr_el1());
1755	write_el1_ctx_common(ctx, mair_el1, read_mair_el1());

222	if (is_feat_trbe_supported()) {
223		trbe_disable_realm(ctx);
224	}
225}
226#endif /* ENABLE_RME && IMAGE_BL31 */
227
228/******************************************************************************
229 * This function performs initializations that are specific to NON-SECURE state
230 * and updates the cpu context specified by 'ctx'.
231 *****************************************************************************/
232static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
233{
234	u_register_t scr_el3;
235	el3_state_t *state;
236
237	state = get_el3state_ctx(ctx);
238	scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
239
240	/* SCR_NS: Set the NS bit */
241	scr_el3 |= SCR_NS_BIT;
242
243	/* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
244	if (is_feat_mte2_supported()) {
245		scr_el3 |= SCR_ATA_BIT;
246	}
247
248	/*
249	 * Pointer Authentication feature, if present, is always enabled by
250	 * default for Non secure lower exception levels. We do not have an
251	 * explicit flag to set it. To prevent the leakage between the worlds
252	 * during world switch, we enable it only for the non-secure world.
253	 *
254	 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
255	 * exception levels of secure and realm worlds.
256	 *
257	 * If the Secure/realm world wants to use pointer authentication,
258	 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
259	 * it will be enabled globally for all the contexts.
260	 *
261	 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
262	 *  other than EL3
263	 *
264	 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
265	 *  than EL3
266	 */
267	if (!is_ctx_pauth_supported()) {
268		scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
269	}
270
271#if HANDLE_EA_EL3_FIRST_NS
272	/* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
273	scr_el3 |= SCR_EA_BIT;
274#endif
275
276#if RAS_TRAP_NS_ERR_REC_ACCESS
277	/*
278	 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
279	 * and RAS ERX registers from EL1 and EL2(from any security state)
280	 * are trapped to EL3.
281	 * Set here to trap only for NS EL1/EL2
282	 */
283	scr_el3 |= SCR_TERR_BIT;
284#endif
285
286	/* CSV2 version 2 and above */
287	if (is_feat_csv2_2_supported()) {
288		/* Enable access to the SCXTNUM_ELx registers. */
289		scr_el3 |= SCR_EnSCXT_BIT;
290	}
291
292#ifdef IMAGE_BL31
293	/*
294	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
295	 *  indicated by the interrupt routing model for BL31.
296	 */
297	scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
298#endif
299
300	if (is_feat_the_supported()) {
301		/* Set the RCWMASKEn bit in SCR_EL3 to enable access to
302		 * RCWMASK_EL1 and RCWSMASK_EL1 registers.
303		 */
304		scr_el3 |= SCR_RCWMASKEn_BIT;
305	}
306
307	if (is_feat_sctlr2_supported()) {
308		/* Set the SCTLR2En bit in SCR_EL3 to enable access to
309		 * SCTLR2_ELx registers.
310		 */
311		scr_el3 |= SCR_SCTLR2En_BIT;
312	}
313
314	if (is_feat_d128_supported()) {
315		/* Set the D128En bit in SCR_EL3 to enable access to 128-bit
316		 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
317		 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
318		 */
319		scr_el3 |= SCR_D128En_BIT;
320	}
321
322	if (is_feat_fpmr_supported()) {
323		/* Set the EnFPM bit in SCR_EL3 to enable access to FPMR
324		 * register.
325		 */
326		scr_el3 |= SCR_EnFPM_BIT;
327	}
328
329	if (is_feat_aie_supported()) {
330		/* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2
331		 * system registers from NS world.
332		 */
333		scr_el3 |= SCR_AIEn_BIT;
334	}
335
336	if (is_feat_pfar_supported()) {
337		/* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR
338		 * system registers from NS world.
339		 */
340		scr_el3 |= SCR_PFAREn_BIT;
341	}
342
343	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
344
345	/* Initialize EL2 context registers */
346#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
347	if (is_feat_hcx_supported()) {
348		/*
349		 * Initialize register HCRX_EL2 with its init value.
350		 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
351		 * chance that this can lead to unexpected behavior in lower
352		 * ELs that have not been updated since the introduction of
353		 * this feature if not properly initialized, especially when
354		 * it comes to those bits that enable/disable traps.
355		 */
356		write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2,
357			HCRX_EL2_INIT_VAL);
358	}
359
360	if (is_feat_fgt_supported()) {
361		/*
362		 * Initialize HFG*_EL2 registers with a default value so legacy
363		 * systems unaware of FEAT_FGT do not get trapped due to their lack
364		 * of initialization for this feature.
365		 */
366		write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2,
367			HFGITR_EL2_INIT_VAL);
368		write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2,
369			HFGRTR_EL2_INIT_VAL);
370		write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2,
371			HFGWTR_EL2_INIT_VAL);
372	}
373#else
374	/* Initialize EL1 context registers */
375	setup_el1_context(ctx, ep);
376#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */

DETAILS

내부 동작을 더 깊게 읽기

IMPLEMENTATION NOTES

구현을 읽을 때 놓치기 쉬운 부분

OBJECT LIFETIME

객체와 수명

FAILURE PATH

실패 지점과 증상

로그가 끊긴 마지막 함수만 고치지 않는다. 그 함수가 받은 주소, size, flag가 만들어진 앞 단계까지 올라가고, 오류 뒤 등록 객체와 hardware 상태가 남았는지도 확인한다.

EVIDENCE

소스 밖에서 확인할 증거

소스 해석은 실제 빌드 산출물과 target 로그로 닫아야 한다. 아래 명령의 보드 이름과 toolchain prefix는 사용 중인 빌드 환경에 맞게 바꾼다.

LAB

직접 확인할 실험

1. 01
   BL33 entry와 U-Boot ELF symbol 대조

   select BL33 진입 전후에 BL33 entry_point_info의 주소·크기·반환값과 timestamp를 함께 남긴다.

2. 02
   ERET 직전 SCR/SPSR/x0-x3 기록

   prepare NS context 진입 전후에 NON_SECURE cpu_context의 주소·크기·반환값과 timestamp를 함께 남긴다.

3. 03
   Linux DT reserved-memory와 secure carveout 비교

   disable init mappings 진입 전후에 SPSR/SCR_EL3의 주소·크기·반환값과 timestamp를 함께 남긴다.

PRIMARY REFERENCES

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